forked from NRZCode/ia32-64
123 lines
4.8 KiB
HTML
123 lines
4.8 KiB
HTML
<!DOCTYPE html>
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>VMPTRST
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— Store Pointer to Virtual-Machine Control Structure</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>VMPTRST
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— Store Pointer to Virtual-Machine Control Structure</h1>
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<table>
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<tr>
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<th>Opcode/Instruction</th>
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<th>Op/En</th>
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<th>Description</th></tr>
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<tr>
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<td>NP 0F C7 /7 VMPTRST m64</td>
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<td>M</td>
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<td>Stores the current VMCS pointer into memory.</td></tr></table>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<td>Op/En</td>
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<td>Operand 1</td>
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<td>Operand 2</td>
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<td>Operand 3</td>
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<td>Operand 4</td></tr>
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<tr>
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<td>M</td>
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<td>ModRM:r/m (w)</td>
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<td>NA</td>
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<td>NA</td>
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<td>NA</td></tr></table>
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<h2 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h2>
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<p>Stores the current-VMCS pointer into a specified memory address. The operand of this instruction is always 64 bits and is always in memory.</p>
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<h2 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h2>
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<pre>IF (register operand) or (not in VMX operation) or (CR0.PE = 0) or (RFLAGS.VM = 1) or (IA32_EFER.LMA = 1 and CS.L = 0)
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THEN #UD;
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ELSIF in VMX non-root operation
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THEN VMexit;
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ELSIF CPL > 0
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THEN #GP(0);
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ELSE
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64-bit in-memory destination operand := current-VMCS pointer;
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VMsucceed;
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FI;
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</pre>
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<h2 id="flags-affected">Flags Affected<a class="anchor" href="#flags-affected">
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¶
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</a></h2>
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<p>See the operation section and Section 31.2.</p>
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<h2 class="exceptions" id="protected-mode-exceptions">Protected Mode Exceptions<a class="anchor" href="#protected-mode-exceptions">
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¶
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</a></h2>
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<table>
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<tr>
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<td rowspan="4">#GP(0)</td>
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<td>If the current privilege level is not 0.</td></tr>
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<tr>
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<td>If the memory destination operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
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<tr>
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<td>If the DS, ES, FS, or GS register contains an unusable segment.</td></tr>
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<tr>
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<td>If the destination operand is located in a read-only data segment or any code segment.</td></tr>
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<tr>
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<td>#PF(fault-code)</td>
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<td>If a page fault occurs in accessing the memory destination operand.</td></tr>
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<tr>
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<td rowspan="2">#SS(0)</td>
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<td>If the memory destination operand effective address is outside the SS segment limit.</td></tr>
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<tr>
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<td>If the SS register contains an unusable segment.</td></tr>
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<tr>
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<td rowspan="2">#UD</td>
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<td>If operand is a register.</td></tr>
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<tr>
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<td>If not in VMX operation.</td></tr></table>
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<h2 class="exceptions" id="real-address-mode-exceptions">Real-Address Mode Exceptions<a class="anchor" href="#real-address-mode-exceptions">
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¶
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</a></h2>
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<table>
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<tr>
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<td>#UD</td>
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<td>The VMPTRST instruction is not recognized in real-address mode.</td></tr></table>
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<h2 class="exceptions" id="virtual-8086-mode-exceptions">Virtual-8086 Mode Exceptions<a class="anchor" href="#virtual-8086-mode-exceptions">
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¶
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</a></h2>
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<table>
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<tr>
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<td>#UD</td>
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<td>The VMPTRST instruction is not recognized in virtual-8086 mode.</td></tr></table>
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<h2 class="exceptions" id="compatibility-mode-exceptions">Compatibility Mode Exceptions<a class="anchor" href="#compatibility-mode-exceptions">
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¶
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</a></h2>
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<table>
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<tr>
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<td>#UD</td>
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<td>The VMPTRST instruction is not recognized in compatibility mode.</td></tr></table>
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<h2 class="exceptions" id="64-bit-mode-exceptions">64-Bit Mode Exceptions<a class="anchor" href="#64-bit-mode-exceptions">
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¶
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</a></h2>
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<table>
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<tr>
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<td rowspan="2">#GP(0)</td>
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<td>If the current privilege level is not 0.</td></tr>
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<tr>
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<td>If the destination operand is in the CS, DS, ES, FS, or GS segments and the memory address is in a non-canonical form.</td></tr>
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<tr>
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<td>#PF(fault-code)</td>
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<td>If a page fault occurs in accessing the memory destination operand.</td></tr>
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<tr>
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<td>#SS(0)</td>
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<td>If the destination operand is in the SS segment and the memory address is in a non-canonical form.</td></tr>
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<tr>
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<td rowspan="2">#UD</td>
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<td>If operand is a register.</td></tr>
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<tr>
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<td>If not in VMX operation.</td></tr></table><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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