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163 lines
7.1 KiB
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>VFPCLASSPH
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— Test Types of Packed FP16 Values</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>VFPCLASSPH
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— Test Types of Packed FP16 Values</h1>
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<table>
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<tr>
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<th> Instruction En Bit Mode Flag
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Support Instruction En Bit Mode Flag
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Support 64/32 CPUID Feature Instruction En Bit Mode Flag CPUID Feature Instruction En Bit Mode Flag Op/ 64/32 CPUID Feature Instruction En Bit Mode Flag 64/32 CPUID Feature Instruction En Bit Mode Flag CPUID Feature Instruction En Bit Mode Flag Op/ 64/32 CPUID Feature </th>
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<th></th>
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<th>Support</th>
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<th></th>
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<th>Description</th></tr>
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<tr>
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<td>EVEX.128.NP.0F3A.W0 66 /r /ib VFPCLASSPH k1{k2}, xmm1/m128/m16bcst, imm8</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX512-FP16 AVX512VL</td>
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<td>Test the input for the following categories: NaN, +0, -0, +Infinity, -Infinity, denormal, finite negative. The immediate field provides a mask bitforeachofthesecategorytests. Themasked test results are OR-ed together to form a mask result.</td></tr>
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<tr>
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<td>EVEX.256.NP.0F3A.W0 66 /r /ib VFPCLASSPH k1{k2}, ymm1/m256/m16bcst, imm8</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX512-FP16 AVX512VL</td>
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<td>Test the input for the following categories: NaN, +0, -0, +Infinity, -Infinity, denormal, finite negative. The immediate field provides a mask bitforeachofthesecategorytests. Themasked test results are OR-ed together to form a mask result.</td></tr>
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<tr>
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<td>EVEX.512.NP.0F3A.W0 66 /r /ib VFPCLASSPH k1{k2}, zmm1/m512/m16bcst, imm8</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX512-FP16</td>
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<td>Test the input for the following categories: NaN, +0, -0, +Infinity, -Infinity, denormal, finite negative. The immediate field provides a mask bitforeachofthesecategorytests. Themasked test results are OR-ed together to form a mask result.</td></tr></table>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Tuple</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Operand 3</th>
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<th>Operand 4</th></tr>
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<tr>
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<td>A</td>
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<td>Full</td>
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<td>ModRM:reg (w)</td>
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<td>ModRM:r/m (r)</td>
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<td>imm8 (r)</td>
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<td>N/A</td></tr></table>
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<h3 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h3>
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<p>This instruction checks the packed FP16 values in the source operand for special categories, specified by the set bits in the imm8 byte. Each set bit in imm8 specifies a category of floating-point values that the input data element is classified against; see <a href='vfpclassph.html#tbl-5-9'>Table 5-9</a> for the categories. The classified results of all specified categories of an input value are ORed together to form the final boolean result for the input element. The result is written to the corresponding bits in the destination mask register according to the writemask.</p>
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<figure id="tbl-5-9">
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<table>
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<tr>
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<th>Bits</th>
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<th>Category</th>
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<th>Classifier</th></tr>
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<tr>
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<td>imm8[0]</td>
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<td>QNAN</td>
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<td>Checks for QNAN</td></tr>
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<tr>
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<td>imm8[1]</td>
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<td>PosZero</td>
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<td>Checks +0</td></tr>
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<tr>
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<td>imm8[2]</td>
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<td>NegZero</td>
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<td>Checks for -0</td></tr>
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<tr>
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<td>imm8[3]</td>
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<td>PosINF</td>
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<td>Checks for +∞</td></tr>
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<tr>
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<td>imm8[4]</td>
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<td>NegINF</td>
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<td>Checks for −∞</td></tr>
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<tr>
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<td>imm8[5]</td>
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<td>Denormal</td>
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<td>Checks for Denormal</td></tr>
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<tr>
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<td>imm8[6]</td>
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<td>Negative</td>
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<td>Checks for Negative finite</td></tr>
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<tr>
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<td>imm8[7]</td>
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<td>SNAN</td>
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<td>Checks for SNAN</td></tr></table>
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<figcaption><a href='vfpclassph.html#tbl-5-9'>Table 5-9</a>. Classifier Operations for VFPCLASSPH/VFPCLASSSH</figcaption></figure>
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<h3 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h3>
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<pre>def check_fp_class_fp16(tsrc, imm8):
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negative := tsrc[15]
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exponent_all_ones := (tsrc[14:10] == 0x1F)
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exponent_all_zeros := (tsrc[14:10] == 0)
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mantissa_all_zeros := (tsrc[9:0] == 0)
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zero := exponent_all_zeros and mantissa_all_zeros
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signaling_bit := tsrc[9]
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snan := exponent_all_ones and not(mantissa_all_zeros) and not(signaling_bit)
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qnan := exponent_all_ones and not(mantissa_all_zeros) and signaling_bit
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positive_zero := not(negative) and zero
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negative_zero := negative and zero
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positive_infinity := not(negative) and exponent_all_ones and mantissa_all_zeros
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negative_infinity := negative and exponent_all_ones and mantissa_all_zeros
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denormal := exponent_all_zeros and not(mantissa_all_zeros)
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finite_negative := negative and not(exponent_all_ones) and not(zero)
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return (imm8[0] and qnan) OR
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(imm8[1] and positive_zero) OR
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(imm8[2] and negative_zero) OR
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(imm8[3] and positive_infinity) OR
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(imm8[4] and negative_infinity) OR
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(imm8[5] and denormal) OR
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(imm8[6] and finite_negative) OR
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(imm8[7] and snan)
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</pre>
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<h4 id="vfpclassph-dest-k2---src--imm8">VFPCLASSPH dest{k2}, src, imm8<a class="anchor" href="#vfpclassph-dest-k2---src--imm8">
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¶
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</a></h4>
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<pre>VL = 128, 256 or 512
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KL := VL/16
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FOR i := 0 to KL-1:
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IF k2[i] or *no writemask*:
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IF SRC is memory and (EVEX.b = 1):
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tsrc := SRC.fp16[0]
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ELSE:
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tsrc := SRC.fp16[i]
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DEST.bit[i] := check_fp_class_fp16(tsrc, imm8)
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ELSE:
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DEST.bit[i] := 0
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DEST[MAXKL-1:kl] := 0
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</pre>
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<h3 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
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¶
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</a></h3>
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<pre>VFPCLASSPH __mmask8 _mm_fpclass_ph_mask (__m128h a, int imm8);
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</pre>
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<pre>VFPCLASSPH __mmask8 _mm_mask_fpclass_ph_mask (__mmask8 k1, __m128h a, int imm8);
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</pre>
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<pre>VFPCLASSPH __mmask16 _mm256_fpclass_ph_mask (__m256h a, int imm8);
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</pre>
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<pre>VFPCLASSPH __mmask16 _mm256_mask_fpclass_ph_mask (__mmask16 k1, __m256h a, int imm8);
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</pre>
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<pre>VFPCLASSPH __mmask32 _mm512_fpclass_ph_mask (__m512h a, int imm8);
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</pre>
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<pre>VFPCLASSPH __mmask32 _mm512_mask_fpclass_ph_mask (__mmask32 k1, __m512h a, int imm8);
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</pre>
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<h3 class="exceptions" id="simd-floating-point-exceptions">SIMD Floating-Point Exceptions<a class="anchor" href="#simd-floating-point-exceptions">
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¶
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</a></h3>
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<p>None.</p>
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<h3 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
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¶
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</a></h3>
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<p>EVEX-encoded instructions, see <span class="not-imported">Table 2-49</span>, “Type E4 Class Exception Conditions.”</p><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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