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155 lines
6.9 KiB
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>VCVTPS2QQ
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— Convert Packed Single Precision Floating-Point Values to Packed SignedQuadword Integer Values</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>VCVTPS2QQ
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— Convert Packed Single Precision Floating-Point Values to Packed SignedQuadword Integer Values</h1>
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<table>
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<tr>
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<th>Opcode/Instruction</th>
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<th>Op / En</th>
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<th>64/32 Bit Mode Support</th>
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<th>CPUID Feature Flag</th>
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<th>Description</th></tr>
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<tr>
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<td>EVEX.128.66.0F.W0 7B /r VCVTPS2QQ xmm1 {k1}{z}, xmm2/m64/m32bcst</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX512VL AVX512DQ</td>
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<td>Convert two packed single precision floating-point values from xmm2/m64/m32bcst to two packed signed quadword values in xmm1 subject to writemask k1.</td></tr>
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<tr>
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<td>EVEX.256.66.0F.W0 7B /r VCVTPS2QQ ymm1 {k1}{z}, xmm2/m128/m32bcst</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX512VL AVX512DQ</td>
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<td>Convert four packed single precision floating-point values from xmm2/m128/m32bcst to four packed signed quadword values in ymm1 subject to writemask k1.</td></tr>
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<tr>
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<td>EVEX.512.66.0F.W0 7B /r VCVTPS2QQ zmm1 {k1}{z}, ymm2/m256/m32bcst{er}</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX512DQ</td>
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<td>Convert eight packed single precision floating-point values from ymm2/m256/m32bcst to eight packed signed quadword values in zmm1 subject to writemask k1.</td></tr></table>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Tuple Type</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Operand 3</th>
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<th>Operand 4</th></tr>
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<tr>
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<td>A</td>
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<td>Half</td>
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<td>ModRM:reg (w)</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td>
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<td>N/A</td></tr></table>
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<h3 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h3>
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<p>Converts eight packed single precision floating-point values in the source operand to eight signed quadword integers in the destination operand.</p>
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<p>When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR register or the embedded rounding control bits. If a converted result cannot be represented in the destination format, the floating-point invalid exception is raised, and if this exception is masked, the indefinite integer value (2<sup>w</sup>-1, where w represents the number of bits in the destination format) is returned.</p>
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<p>The source operand is a YMM/XMM/XMM (low 64- bits) register or a 256/128/64-bit memory location. The destination operation is a ZMM/YMM/XMM register conditionally updated with writemask k1.</p>
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<p>Note: EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.</p>
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<h3 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h3>
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<h4 id="vcvtps2qq--evex-encoded-versions--when-src-operand-is-a-register">VCVTPS2QQ (EVEX Encoded Versions) When SRC Operand is a Register<a class="anchor" href="#vcvtps2qq--evex-encoded-versions--when-src-operand-is-a-register">
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¶
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</a></h4>
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<pre>(KL, VL) = (2, 128), (4, 256), (8, 512)
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IF (VL == 512) AND (EVEX.b == 1)
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THEN
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SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(EVEX.RC);
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ELSE
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SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(MXCSR.RC);
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FI;
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FOR j := 0 TO KL-1
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i := j * 64
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k := j * 32
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IF k1[j] OR *no writemask*
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THEN DEST[i+63:i] :=
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Convert_Single_Precision_To_QuadInteger(SRC[k+31:k])
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ELSE
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IF *merging-masking* ; merging-masking
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THEN *DEST[i+63:i] remains unchanged*
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ELSE ; zeroing-masking
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DEST[i+63:i] := 0
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FI
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FI;
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ENDFOR
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DEST[MAXVL-1:VL] := 0
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</pre>
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<h4 id="vcvtps2qq--evex-encoded-versions--when-src-operand-is-a-memory-source">VCVTPS2QQ (EVEX Encoded Versions) When SRC Operand is a Memory Source<a class="anchor" href="#vcvtps2qq--evex-encoded-versions--when-src-operand-is-a-memory-source">
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¶
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</a></h4>
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<pre>(KL, VL) = (2, 128), (4, 256), (8, 512)
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FOR j := 0 TO KL-1
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i := j * 64
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k := j * 32
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IF k1[j] OR *no writemask*
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THEN
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IF (EVEX.b == 1)
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THEN
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DEST[i+63:i] :=
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Convert_Single_Precision_To_QuadInteger(SRC[31:0])
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ELSE
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DEST[i+63:i] :=
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Convert_Single_Precision_To_QuadInteger(SRC[k+31:k])
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FI;
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ELSE
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IF *merging-masking* ; merging-masking
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THEN *DEST[i+63:i] remains unchanged*
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ELSE ; zeroing-masking
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DEST[i+63:i] := 0
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FI
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FI;
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ENDFOR
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DEST[MAXVL-1:VL] := 0
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</pre>
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<h3 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
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¶
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</a></h3>
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<pre>VCVTPS2QQ __m512i _mm512_cvtps_epi64( __m512 a);
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</pre>
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<pre>VCVTPS2QQ __m512i _mm512_mask_cvtps_epi64( __m512i s, __mmask16 k, __m512 a);
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</pre>
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<pre>VCVTPS2QQ __m512i _mm512_maskz_cvtps_epi64( __mmask16 k, __m512 a);
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</pre>
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<pre>VCVTPS2QQ __m512i _mm512_cvt_roundps_epi64( __m512 a, int r);
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</pre>
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<pre>VCVTPS2QQ __m512i _mm512_mask_cvt_roundps_epi64( __m512i s, __mmask16 k, __m512 a, int r);
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</pre>
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<pre>VCVTPS2QQ __m512i _mm512_maskz_cvt_roundps_epi64( __mmask16 k, __m512 a, int r);
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</pre>
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<pre>VCVTPS2QQ __m256i _mm256_cvtps_epi64( __m256 a);
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</pre>
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<pre>VCVTPS2QQ __m256i _mm256_mask_cvtps_epi64( __m256i s, __mmask8 k, __m256 a);
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</pre>
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<pre>VCVTPS2QQ __m256i _mm256_maskz_cvtps_epi64( __mmask8 k, __m256 a);
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</pre>
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<pre>VCVTPS2QQ __m128i _mm_cvtps_epi64( __m128 a);
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</pre>
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<pre>VCVTPS2QQ __m128i _mm_mask_cvtps_epi64( __m128i s, __mmask8 k, __m128 a);
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</pre>
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<pre>VCVTPS2QQ __m128i _mm_maskz_cvtps_epi64( __mmask8 k, __m128 a);
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</pre>
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<h3 class="exceptions" id="simd-floating-point-exceptions">SIMD Floating-Point Exceptions<a class="anchor" href="#simd-floating-point-exceptions">
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¶
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</a></h3>
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<p>Invalid, Precision.</p>
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<h3 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
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¶
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</a></h3>
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<p>EVEX-encoded instructions, see <span class="not-imported">Table 2-47</span>, “Type E3 Class Exception Conditions.”</p>
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<p>Additionally:</p>
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<table>
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<tr>
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<td>#UD</td>
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<td>If EVEX.vvvv != 1111B.</td></tr></table><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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