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300 lines
19 KiB
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<!DOCTYPE html>
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>VCVTPS2PH
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— Convert Single-Precision FP Value to 16-bit FP Value</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>VCVTPS2PH
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— Convert Single-Precision FP Value to 16-bit FP Value</h1>
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<table>
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<tr>
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<th>Opcode/Instruction</th>
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<th>Op/En</th>
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<th>64/32 Bit Mode Support</th>
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<th>CPUID Feature Flag</th>
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<th>Description</th></tr>
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<tr>
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<td>VEX.128.66.0F3A.W0 1D /r ib VCVTPS2PH xmm1/m64, xmm2, imm8</td>
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<td>A</td>
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<td>V/V</td>
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<td>F16C</td>
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<td>Convert four packed single-precision floating-point values in xmm2 to packed half-precision (16-bit) floating-point values in xmm1/m64. Imm8 provides rounding controls.</td></tr>
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<tr>
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<td>VEX.256.66.0F3A.W0 1D /r ib VCVTPS2PH xmm1/m128, ymm2, imm8</td>
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<td>A</td>
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<td>V/V</td>
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<td>F16C</td>
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<td>Convert eight packed single-precision floating-point values in ymm2 to packed half-precision (16-bit) floating-point values in xmm1/m128. Imm8 provides rounding controls.</td></tr>
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<tr>
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<td>EVEX.128.66.0F3A.W0 1D /r ib VCVTPS2PH xmm1/m64 {k1}{z}, xmm2, imm8</td>
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<td>B</td>
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<td>V/V</td>
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<td>AVX512VL AVX512F</td>
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<td>Convert four packed single-precision floating-point values in xmm2 to packed half-precision (16-bit) floating-point values in xmm1/m64. Imm8 provides rounding controls.</td></tr>
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<tr>
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<td>EVEX.256.66.0F3A.W0 1D /r ib VCVTPS2PH xmm1/m128 {k1}{z}, ymm2, imm8</td>
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<td>B</td>
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<td>V/V</td>
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<td>AVX512VL AVX512F</td>
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<td>Convert eight packed single-precision floating-point values in ymm2 to packed half-precision (16-bit) floating-point values in xmm1/m128. Imm8 provides rounding controls.</td></tr>
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<tr>
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<td>EVEX.512.66.0F3A.W0 1D /r ib VCVTPS2PH ymm1/m256 {k1}{z}, zmm2{sae}, imm8</td>
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<td>B</td>
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<td>V/V</td>
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<td>AVX512F</td>
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<td>Convert sixteen packed single-precision floating-point values in zmm2 to packed half-precision (16-bit) floating-point values in ymm1/m256. Imm8 provides rounding controls.</td></tr></table>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Tuple Type</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Operand 3</th>
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<th>Operand 4</th></tr>
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<tr>
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<td>A</td>
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<td>N/A</td>
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<td>ModRM:r/m (w)</td>
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<td>ModRM:reg (r)</td>
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<td>imm8</td>
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<td>N/A</td></tr>
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<tr>
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<td>B</td>
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<td>Half Mem</td>
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<td>ModRM:r/m (w)</td>
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<td>ModRM:reg (r)</td>
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<td>imm8</td>
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<td>N/A</td></tr></table>
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<h3 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h3>
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<p>Convert packed single-precision floating values in the source operand to half-precision (16-bit) floating-point values and store to the destination operand. The rounding mode is specified using the immediate field (imm8).</p>
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<p>Underflow results (i.e., tiny results) are converted to denormals. MXCSR.FTZ is ignored. If a source element is denormal relative to the input format with DM masked and at least one of PM or UM unmasked; a SIMD exception will be raised with DE, UE and PE set.</p>
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<figure id="fig-5-7">
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<figcaption><a href='vcvtps2ph.html#fig-5-7'>Figure 5-7</a>. VCVTPS2PH (128-bit Version)</figcaption></figure>
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<p>The immediate byte defines several bit fields that control rounding operation. The effect and encoding of the RC field are listed in <a href='vcvtps2ph.html#tbl-5-13'>Table 5-13</a>.</p>
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<figure id="tbl-5-13">
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<table>
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<tr>
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<th>Bits</th>
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<th>Field Name/value</th>
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<th>Description</th>
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<th>Comment</th></tr>
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<tr>
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<td rowspan="4">Imm[1:0]</td>
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<td>RC=00B</td>
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<td>Round to nearest even</td>
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<td rowspan="4">If Imm[2] = 0</td></tr>
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<tr>
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<td>RC=01B</td>
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<td>Round down</td></tr>
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<tr>
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<td>RC=10B</td>
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<td>Round up</td></tr>
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<tr>
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<td>RC=11B</td>
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<td>Truncate</td></tr>
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<tr>
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<td rowspan="2">Imm[2]</td>
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<td>MS1=0</td>
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<td>Use imm[1:0] for rounding</td>
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<td>Ignore MXCSR.RC</td></tr>
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<tr>
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<td>MS1=1</td>
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<td>Use MXCSR.RC for rounding</td>
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<td></td></tr>
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<tr>
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<td>Imm[7:3]</td>
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<td>Ignored</td>
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<td>Ignored by processor</td>
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<td></td></tr></table>
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<figcaption><a href='vcvtps2ph.html#tbl-5-13'>Table 5-13</a>. Immediate Byte Encoding for 16-bit Floating-Point Conversion Instructions</figcaption></figure>
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<p>VEX.128 version: The source operand is a XMM register. The destination operand is a XMM register or 64-bit memory location. If the destination operand is a register then the upper bits (MAXVL-1:64) of corresponding register are zeroed.</p>
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<p>VEX.256 version: The source operand is a YMM register. The destination operand is a XMM register or 128-bit memory location. If the destination operand is a register, the upper bits (MAXVL-1:128) of the corresponding destination register are zeroed.</p>
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<p>Note: VEX.vvvv and EVEX.vvvv are reserved (must be 1111b).</p>
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<p>EVEX encoded versions: The source operand is a ZMM/YMM/XMM register. The destination operand is a YMM/XMM/XMM (low 64-bits) register or a 256/128/64-bit memory location, conditionally updated with writemask k1. Bits (MAXVL-1:256/128/64) of the corresponding destination register are zeroed.</p>
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<h3 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h3>
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<pre>vCvt_s2h(SRC1[31:0])
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{
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IF Imm[2] = 0
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THEN ; using Imm[1:0] for rounding control, see <a href='vcvtps2ph.html#tbl-5-13'>Table 5-13</a>
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RETURN Cvt_Single_Precision_To_Half_Precision_FP_Imm(SRC1[31:0]);
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ELSE ; using MXCSR.RC for rounding control
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RETURN Cvt_Single_Precision_To_Half_Precision_FP_Mxcsr(SRC1[31:0]);
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FI;
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}
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</pre>
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<h4 id="vcvtps2ph--evex-encoded-versions--when-dest-is-a-register">VCVTPS2PH (EVEX Encoded Versions) When DEST is a Register<a class="anchor" href="#vcvtps2ph--evex-encoded-versions--when-dest-is-a-register">
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¶
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</a></h4>
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<pre>(KL, VL) = (4, 128), (8, 256), (16, 512)
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FOR j := 0 TO KL-1
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i := j * 16
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k := j * 32
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IF k1[j] OR *no writemask*
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THEN DEST[i+15:i] :=
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vCvt_s2h(SRC[k+31:k])
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ELSE
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IF *merging-masking*
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; merging-masking
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THEN *DEST[i+15:i] remains unchanged*
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ELSE
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; zeroing-masking
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DEST[i+15:i] := 0
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FI
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FI;
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ENDFOR
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DEST[MAXVL-1:VL/2] := 0
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</pre>
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<h4 id="vcvtps2ph--evex-encoded-versions--when-dest-is-memory">VCVTPS2PH (EVEX Encoded Versions) When DEST is Memory<a class="anchor" href="#vcvtps2ph--evex-encoded-versions--when-dest-is-memory">
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¶
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</a></h4>
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<pre>(KL, VL) = (4, 128), (8, 256), (16, 512)
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FOR j := 0 TO KL-1
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i := j * 16
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k := j * 32
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IF k1[j] OR *no writemask*
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THEN DEST[i+15:i] :=
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vCvt_s2h(SRC[k+31:k])
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ELSE
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*DEST[i+15:i] remains unchanged*
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; merging-masking
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FI;
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ENDFOR
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</pre>
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<h4 id="vcvtps2ph--vex-256-encoded-version-">VCVTPS2PH (VEX.256 Encoded Version)<a class="anchor" href="#vcvtps2ph--vex-256-encoded-version-">
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¶
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</a></h4>
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<pre>DEST[15:0] := vCvt_s2h(SRC1[31:0]);
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DEST[31:16] := vCvt_s2h(SRC1[63:32]);
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DEST[47:32] := vCvt_s2h(SRC1[95:64]);
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DEST[63:48] := vCvt_s2h(SRC1[127:96]);
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DEST[79:64] := vCvt_s2h(SRC1[159:128]);
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DEST[95:80] := vCvt_s2h(SRC1[191:160]);
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DEST[111:96] := vCvt_s2h(SRC1[223:192]);
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DEST[127:112] := vCvt_s2h(SRC1[255:224]);
|
||
DEST[MAXVL-1:128] := 0
|
||
</pre>
|
||
<h4 id="vcvtps2ph--vex-128-encoded-version-">VCVTPS2PH (VEX.128 Encoded Version)<a class="anchor" href="#vcvtps2ph--vex-128-encoded-version-">
|
||
¶
|
||
</a></h4>
|
||
<pre>DEST[15:0] := vCvt_s2h(SRC1[31:0]);
|
||
DEST[31:16] := vCvt_s2h(SRC1[63:32]);
|
||
DEST[47:32] := vCvt_s2h(SRC1[95:64]);
|
||
DEST[63:48] := vCvt_s2h(SRC1[127:96]);
|
||
DEST[MAXVL-1:64] := 0
|
||
</pre>
|
||
<h3 id="flags-affected">Flags Affected<a class="anchor" href="#flags-affected">
|
||
¶
|
||
</a></h3>
|
||
<p>None.</p>
|
||
<h3 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
|
||
¶
|
||
</a></h3>
|
||
<pre>VCVTPS2PH __m256i _mm512_cvtps_ph(__m512 a);
|
||
</pre>
|
||
<pre>VCVTPS2PH __m256i _mm512_mask_cvtps_ph(__m256i s, __mmask16 k,__m512 a);
|
||
</pre>
|
||
<pre>VCVTPS2PH __m256i _mm512_maskz_cvtps_ph(__mmask16 k,__m512 a);
|
||
</pre>
|
||
<pre>VCVTPS2PH __m256i _mm512_cvt_roundps_ph(__m512 a, const int imm);
|
||
</pre>
|
||
<pre>VCVTPS2PH __m256i _mm512_mask_cvt_roundps_ph(__m256i s, __mmask16 k,__m512 a, const int imm);
|
||
</pre>
|
||
<pre>VCVTPS2PH __m256i _mm512_maskz_cvt_roundps_ph(__mmask16 k,__m512 a, const int imm);
|
||
</pre>
|
||
<pre>VCVTPS2PH __m128i _mm256_mask_cvtps_ph(__m128i s, __mmask8 k,__m256 a);
|
||
</pre>
|
||
<pre>VCVTPS2PH __m128i _mm256_maskz_cvtps_ph(__mmask8 k,__m256 a);
|
||
</pre>
|
||
<pre>VCVTPS2PH __m128i _mm_mask_cvtps_ph(__m128i s, __mmask8 k,__m128 a);
|
||
</pre>
|
||
<pre>VCVTPS2PH __m128i _mm_maskz_cvtps_ph(__mmask8 k,__m128 a);
|
||
</pre>
|
||
<pre>VCVTPS2PH __m128i _mm_cvtps_ph ( __m128 m1, const int imm);
|
||
</pre>
|
||
<pre>VCVTPS2PH __m128i _mm256_cvtps_ph(__m256 m1, const int imm);
|
||
</pre>
|
||
<h3 class="exceptions" id="simd-floating-point-exceptions">SIMD Floating-Point Exceptions<a class="anchor" href="#simd-floating-point-exceptions">
|
||
¶
|
||
</a></h3>
|
||
<p>Invalid, Underflow, Overflow, Precision, Denormal (if MXCSR.DAZ=0).</p>
|
||
<h3 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
|
||
¶
|
||
</a></h3>
|
||
<p>VEX-encoded instructions, see <span class="not-imported">Table 2-26</span>, “Type 11 Class Exception Conditions” (do not report #AC);</p>
|
||
<p>EVEX-encoded instructions, see <span class="not-imported">Table 2-60</span>, “Type E11 Class Exception Conditions.”</p>
|
||
<p>Additionally:</p>
|
||
<table>
|
||
<tr>
|
||
<td>#UD</td>
|
||
<td>If VEX.W=1.</td></tr>
|
||
<tr>
|
||
<td>#UD</td>
|
||
<td>If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.</td></tr></table><footer><p>
|
||
This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
|
||
inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
|
||
ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
|
||
</p></footer></body></html>
|