forked from NRZCode/ia32-64
119 lines
5.6 KiB
HTML
119 lines
5.6 KiB
HTML
<!DOCTYPE html>
|
||
<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>VCVTPH2QQ
|
||
— Convert Packed FP16 Values to Signed Quadword Integer Values</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>VCVTPH2QQ
|
||
— Convert Packed FP16 Values to Signed Quadword Integer Values</h1>
|
||
|
||
<table>
|
||
<tr>
|
||
<th> Instruction En Bit Mode Flag
|
||
Support Instruction En Bit Mode Flag
|
||
Support 64/32 CPUID Feature Instruction En Bit Mode Flag CPUID Feature Instruction En Bit Mode Flag Op/ 64/32 CPUID Feature Instruction En Bit Mode Flag 64/32 CPUID Feature Instruction En Bit Mode Flag CPUID Feature Instruction En Bit Mode Flag Op/ 64/32 CPUID Feature </th>
|
||
<th></th>
|
||
<th>Support</th>
|
||
<th></th>
|
||
<th>Description</th></tr>
|
||
<tr>
|
||
<td>EVEX.128.66.MAP5.W0 7B /r VCVTPH2QQ xmm1{k1}{z}, xmm2/m32/m16bcst</td>
|
||
<td>A</td>
|
||
<td>V/V</td>
|
||
<td>AVX512-FP16 AVX512VL</td>
|
||
<td>Convert two packed FP16 values in xmm2/m32/m16bcst to two signed quadword integers, and store the result in xmm1 subject to writemask k1.</td></tr>
|
||
<tr>
|
||
<td>EVEX.256.66.MAP5.W0 7B /r VCVTPH2QQ ymm1{k1}{z}, xmm2/m64/m16bcst</td>
|
||
<td>A</td>
|
||
<td>V/V</td>
|
||
<td>AVX512-FP16 AVX512VL</td>
|
||
<td>Convert four packed FP16 values in xmm2/m64/m16bcst to four signed quadword integers, and store the result in ymm1 subject to writemask k1.</td></tr>
|
||
<tr>
|
||
<td>EVEX.512.66.MAP5.W0 7B /r VCVTPH2QQ zmm1{k1}{z}, xmm2/m128/m16bcst {er}</td>
|
||
<td>A</td>
|
||
<td>V/V</td>
|
||
<td>AVX512-FP16</td>
|
||
<td>Convert eight packed FP16 values in xmm2/m128/m16bcst to eight signed quadword integers, and store the result in zmm1 subject to writemask k1.</td></tr></table>
|
||
<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
|
||
¶
|
||
</a></h2>
|
||
<table>
|
||
<tr>
|
||
<th>Op/En</th>
|
||
<th>Tuple</th>
|
||
<th>Operand 1</th>
|
||
<th>Operand 2</th>
|
||
<th>Operand 3</th>
|
||
<th>Operand 4</th></tr>
|
||
<tr>
|
||
<td>A</td>
|
||
<td>Quarter</td>
|
||
<td>ModRM:reg (w)</td>
|
||
<td>ModRM:r/m (r)</td>
|
||
<td>N/A</td>
|
||
<td>N/A</td></tr></table>
|
||
<h3 id="description">Description<a class="anchor" href="#description">
|
||
¶
|
||
</a></h3>
|
||
<p>This instruction converts packed FP16 values in the source operand to signed quadword integers in destination operand.</p>
|
||
<p>When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR register or the embedded rounding control bits. If a converted result cannot be represented in the destination format, the floating-point invalid exception is raised, and if this exception is masked, the indefinite integer value is returned.</p>
|
||
<p>The destination elements are updated according to the writemask.</p>
|
||
<h3 id="operation">Operation<a class="anchor" href="#operation">
|
||
¶
|
||
</a></h3>
|
||
<h4 id="vcvtph2qq-dest--src">VCVTPH2QQ DEST, SRC<a class="anchor" href="#vcvtph2qq-dest--src">
|
||
¶
|
||
</a></h4>
|
||
<pre>VL = 128, 256 or 512
|
||
KL := VL / 64
|
||
IF *SRC is a register* and (VL = 512) and (EVEX.b = 1):
|
||
SET_RM(EVEX.RC)
|
||
ELSE:
|
||
SET_RM(MXCSR.RC)
|
||
FOR j := 0 TO KL-1:
|
||
IF k1[j] OR *no writemask*:
|
||
IF *SRC is memory* and EVEX.b = 1:
|
||
tsrc := SRC.fp16[0]
|
||
ELSE
|
||
tsrc := SRC.fp16[j]
|
||
DEST.qword[j] := Convert_fp16_to_integer64(tsrc)
|
||
ELSE IF *zeroing*:
|
||
DEST.qword[j] := 0
|
||
// else dest.qword[j] remains unchanged
|
||
DEST[MAXVL-1:VL] := 0
|
||
</pre>
|
||
<h3 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
|
||
¶
|
||
</a></h3>
|
||
<pre>VCVTPH2QQ __m512i _mm512_cvt_roundph_epi64 (__m128h a, int rounding);
|
||
</pre>
|
||
<pre>VCVTPH2QQ __m512i _mm512_mask_cvt_roundph_epi64 (__m512i src, __mmask8 k, __m128h a, int rounding);
|
||
</pre>
|
||
<pre>VCVTPH2QQ __m512i _mm512_maskz_cvt_roundph_epi64 (__mmask8 k, __m128h a, int rounding);
|
||
</pre>
|
||
<pre>VCVTPH2QQ __m128i _mm_cvtph_epi64 (__m128h a);
|
||
</pre>
|
||
<pre>VCVTPH2QQ __m128i _mm_mask_cvtph_epi64 (__m128i src, __mmask8 k, __m128h a);
|
||
</pre>
|
||
<pre>VCVTPH2QQ __m128i _mm_maskz_cvtph_epi64 (__mmask8 k, __m128h a);
|
||
</pre>
|
||
<pre>VCVTPH2QQ __m256i _mm256_cvtph_epi64 (__m128h a);
|
||
</pre>
|
||
<pre>VCVTPH2QQ __m256i _mm256_mask_cvtph_epi64 (__m256i src, __mmask8 k, __m128h a);
|
||
</pre>
|
||
<pre>VCVTPH2QQ __m256i _mm256_maskz_cvtph_epi64 (__mmask8 k, __m128h a);
|
||
</pre>
|
||
<pre>VCVTPH2QQ __m512i _mm512_cvtph_epi64 (__m128h a);
|
||
</pre>
|
||
<pre>VCVTPH2QQ __m512i _mm512_mask_cvtph_epi64 (__m512i src, __mmask8 k, __m128h a);
|
||
</pre>
|
||
<pre>VCVTPH2QQ __m512i _mm512_maskz_cvtph_epi64 (__mmask8 k, __m128h a);
|
||
</pre>
|
||
<h3 class="exceptions" id="simd-floating-point-exceptions">SIMD Floating-Point Exceptions<a class="anchor" href="#simd-floating-point-exceptions">
|
||
¶
|
||
</a></h3>
|
||
<p>Invalid, Precision.</p>
|
||
<h3 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
|
||
¶
|
||
</a></h3>
|
||
<p>EVEX-encoded instructions, see <span class="not-imported">Table 2-46</span>, “Type E2 Class Exception Conditions.”</p><footer><p>
|
||
This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
|
||
inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
|
||
ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
|
||
</p></footer></body></html>
|