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112 lines
4.8 KiB
HTML
<!DOCTYPE html>
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>VCMPSH
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— Compare Scalar FP16 Values</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>VCMPSH
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— Compare Scalar FP16 Values</h1>
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<table>
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<tr>
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<th> Instruction En Bit Mode Flag
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Support Instruction En Bit Mode Flag
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Support 64/32 CPUID Feature Instruction En Bit Mode Flag CPUID Feature Instruction En Bit Mode Flag Op/ 64/32 CPUID Feature Instruction En Bit Mode Flag 64/32 CPUID Feature Instruction En Bit Mode Flag CPUID Feature Instruction En Bit Mode Flag Op/ 64/32 CPUID Feature </th>
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<th></th>
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<th>Support</th>
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<th></th>
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<th>Description</th></tr>
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<tr>
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<td>EVEX.LLIG.F3.0F3A.W0 C2 /r /ib VCMPSH k1{k2}, xmm2, xmm3/m16 {sae}, imm8</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX512-FP16</td>
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<td>Compare low FP16 values in xmm3/m16 and xmm2 using bits 4:0 of imm8 as a comparison predicate subject to writemask k2, and store the result in mask register k1.</td></tr></table>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Tuple</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Operand 3</th>
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<th>Operand 4</th></tr>
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<tr>
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<td>A</td>
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<td>Scalar</td>
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<td>ModRM:reg (w)</td>
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<td>VEX.vvvv (r)</td>
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<td>ModRM:r/m (r)</td>
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<td>imm8 (r)</td></tr></table>
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<h3 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h3>
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<p>This instruction compares the FP16 values from the lowest element of the source operands and stores the result in the destination mask operand. The comparison predicate operand (immediate byte bits 4:0) specifies the type of comparison performed on the pair of packed FP16 values. The low destination bit is updated according to the writemask. Bits MAXKL-1:1 of the destination operand are zeroed.</p>
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<h3 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h3>
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<pre>CASE (imm8 & 0x1F) OF
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0: CMP_OPERATOR := EQ_OQ;
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1: CMP_OPERATOR := LT_OS;
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2: CMP_OPERATOR := LE_OS;
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3: CMP_OPERATOR := UNORD_Q;
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4: CMP_OPERATOR := NEQ_UQ;
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5: CMP_OPERATOR := NLT_US;
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6: CMP_OPERATOR := NLE_US;
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7: CMP_OPERATOR := ORD_Q;
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8: CMP_OPERATOR := EQ_UQ;
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9: CMP_OPERATOR := NGE_US;
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10: CMP_OPERATOR := NGT_US;
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11: CMP_OPERATOR := FALSE_OQ;
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12: CMP_OPERATOR := NEQ_OQ;
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13: CMP_OPERATOR := GE_OS;
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14: CMP_OPERATOR := GT_OS;
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15: CMP_OPERATOR := TRUE_UQ;
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16: CMP_OPERATOR := EQ_OS;
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17: CMP_OPERATOR := LT_OQ;
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18: CMP_OPERATOR := LE_OQ;
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19: CMP_OPERATOR := UNORD_S;
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20: CMP_OPERATOR := NEQ_US;
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21: CMP_OPERATOR := NLT_UQ;
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22: CMP_OPERATOR := NLE_UQ;
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23: CMP_OPERATOR := ORD_S;
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24: CMP_OPERATOR := EQ_US;
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25: CMP_OPERATOR := NGE_UQ;
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26: CMP_OPERATOR := NGT_UQ;
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27: CMP_OPERATOR := FALSE_OS;
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28: CMP_OPERATOR := NEQ_OS;
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29: CMP_OPERATOR := GE_OQ;
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30: CMP_OPERATOR := GT_OQ;
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31: CMP_OPERATOR := TRUE_US;
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ESAC
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</pre>
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<h4 id="vcmpsh--evex-encoded-versions-">VCMPSH (EVEX Encoded Versions)<a class="anchor" href="#vcmpsh--evex-encoded-versions-">
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¶
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</a></h4>
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<pre>IF k2[0] OR *no writemask*:
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DEST.bit[0] := SRC1.fp16[0] CMP_OPERATOR SRC2.fp16[0]
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ELSE
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DEST.bit[0] := 0
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DEST[MAXKL-1:1] := 0
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</pre>
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<h3 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
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¶
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</a></h3>
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<pre>VCMPSH __mmask8 _mm_cmp_round_sh_mask (__m128h a, __m128h b, const int imm8, const int sae);
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</pre>
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<pre>VCMPSH __mmask8 _mm_mask_cmp_round_sh_mask (__mmask8 k1, __m128h a, __m128h b, const int imm8, const int sae);
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</pre>
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<pre>VCMPSH __mmask8 _mm_cmp_sh_mask (__m128h a, __m128h b, const int imm8);
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</pre>
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<pre>VCMPSH __mmask8 _mm_mask_cmp_sh_mask (__mmask8 k1, __m128h a, __m128h b, const int imm8);
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</pre>
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<h3 class="exceptions" id="simd-floating-point-exceptions">SIMD Floating-Point Exceptions<a class="anchor" href="#simd-floating-point-exceptions">
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¶
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</a></h3>
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<p>Invalid, Denormal.</p>
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<h3 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
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¶
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</a></h3>
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<p>EVEX-encoded instructions, see <span class="not-imported">Table 2-47</span>, “Type E3 Class Exception Conditions.”</p><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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