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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>VALIGND/VALIGNQ
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— Align Doubleword/Quadword Vectors</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>VALIGND/VALIGNQ
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— Align Doubleword/Quadword Vectors</h1>
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<table>
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<tr>
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<th>Opcode/Instruction</th>
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<th>Op/En</th>
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<th>64/32 Bit Mode Support</th>
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<th>CPUID Feature Flag</th>
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<th>Description</th></tr>
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<tr>
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<td>EVEX.128.66.0F3A.W0 03 /r ib VALIGND xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcst, imm8</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX512VL AVX512F</td>
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<td>Shift right and merge vectors xmm2 and xmm3/m128/m32bcst with double-word granularity using imm8 as number of elements to shift, and store the final result in xmm1, under writemask.</td></tr>
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<tr>
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<td>EVEX.128.66.0F3A.W1 03 /r ib VALIGNQ xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcst, imm8</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX512VL AVX512F</td>
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<td>Shift right and merge vectors xmm2 and xmm3/m128/m64bcst with quad-word granularity using imm8 as number of elements to shift, and store the final result in xmm1, under writemask.</td></tr>
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<tr>
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<td>EVEX.256.66.0F3A.W0 03 /r ib VALIGND ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcst, imm8</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX512VL AVX512F</td>
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<td>Shift right and merge vectors ymm2 and ymm3/m256/m32bcst with double-word granularity using imm8 as number of elements to shift, and store the final result in ymm1, under writemask.</td></tr>
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<tr>
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<td>EVEX.256.66.0F3A.W1 03 /r ib VALIGNQ ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcst, imm8</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX512VL AVX512F</td>
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<td>Shift right and merge vectors ymm2 and ymm3/m256/m64bcst with quad-word granularity using imm8 as number of elements to shift, and store the final result in ymm1, under writemask.</td></tr>
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<tr>
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<td>EVEX.512.66.0F3A.W0 03 /r ib VALIGND zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst, imm8</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX512F</td>
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<td>Shift right and merge vectors zmm2 and zmm3/m512/m32bcst with double-word granularity using imm8 as number of elements to shift, and store the final result in zmm1, under writemask.</td></tr>
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<tr>
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<td>EVEX.512.66.0F3A.W1 03 /r ib VALIGNQ zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst, imm8</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX512F</td>
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<td>Shift right and merge vectors zmm2 and zmm3/m512/m64bcst with quad-word granularity using imm8 as number of elements to shift, and store the final result in zmm1, under writemask.</td></tr></table>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Tuple Type</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Operand 3</th>
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<th>Operand 4</th></tr>
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<tr>
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<td>A</td>
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<td>Full</td>
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<td>ModRM:reg (w)</td>
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<td>EVEX.vvvv (r)</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td></tr></table>
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<h3 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h3>
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<p>Concatenates and shifts right doubleword/quadword elements of the first source operand (the second operand) and the second source operand (the third operand) into a 1024/512/256-bit intermediate vector. The low 512/256/128-bit of the intermediate vector is written to the destination operand (the first operand) using the writemask k1. The destination and first source operands are ZMM/YMM/XMM registers. The second source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 32/64-bit memory location.</p>
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<p>This instruction is writemasked, so only those elements with the corresponding bit set in vector mask register k1 are computed and stored into zmm1. Elements in zmm1 with the corresponding bit clear in k1 retain their previous values (merging-masking) or are set to 0 (zeroing-masking).</p>
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<h3 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h3>
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<h4 id="valignd--evex-encoded-versions-">VALIGND (EVEX Encoded Versions)<a class="anchor" href="#valignd--evex-encoded-versions-">
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¶
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</a></h4>
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<pre>(KL, VL) = (4, 128), (8, 256), (16, 512)
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IF (SRC2 *is memory*) (AND EVEX.b = 1)
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THEN
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FOR j := 0 TO KL-1
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i := j * 32
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src[i+31:i] := SRC2[31:0]
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ENDFOR;
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ELSE src := SRC2
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FI
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; Concatenate sources
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tmp[VL-1:0] := src[VL-1:0]
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tmp[2VL-1:VL] := SRC1[VL-1:0]
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; Shift right doubleword elements
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IF VL = 128
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THEN SHIFT = imm8[1:0]
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ELSE
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IF VL = 256
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THEN SHIFT = imm8[2:0]
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ELSE SHIFT = imm8[3:0]
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FI
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FI;
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tmp[2VL-1:0] := tmp[2VL-1:0] >> (32*SHIFT)
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; Apply writemask
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FOR j := 0 TO KL-1
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i := j * 32
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IF k1[j] OR *no writemask*
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THEN DEST[i+31:i] := tmp[i+31:i]
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ELSE
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IF *merging-masking*
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THEN *DEST[i+31:i] remains unchanged*
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ELSE ; zeroing-masking
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DEST[i+31:i] := 0
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FI
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FI;
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ENDFOR;
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DEST[MAXVL-1:VL] := 0
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</pre>
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<h4 id="valignq--evex-encoded-versions-">VALIGNQ (EVEX Encoded Versions)<a class="anchor" href="#valignq--evex-encoded-versions-">
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¶
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</a></h4>
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<pre>(KL, VL) = (2, 128), (4, 256),(8, 512)
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IF (SRC2 *is memory*) (AND EVEX.b = 1)
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THEN
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FOR j := 0 TO KL-1
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i := j * 64
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src[i+63:i] := SRC2[63:0]
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ENDFOR;
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ELSE src := SRC2
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FI
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; Concatenate sources
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tmp[VL-1:0] := src[VL-1:0]
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tmp[2VL-1:VL] := SRC1[VL-1:0]
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; Shift right quadword elements
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IF VL = 128
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THEN SHIFT = imm8[0]
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ELSE
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IF VL = 256
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THEN SHIFT = imm8[1:0]
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ELSE SHIFT = imm8[2:0]
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FI
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FI;
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tmp[2VL-1:0] := tmp[2VL-1:0] >> (64*SHIFT)
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; Apply writemask
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FOR j := 0 TO KL-1
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i := j * 64
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IF k1[j] OR *no writemask*
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THEN DEST[i+63:i] := tmp[i+63:i]
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ELSE
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IF *merging-masking*
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THEN *DEST[i+63:i] remains unchanged*
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ELSE ; zeroing-masking
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DEST[i+63:i] := 0
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FI
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FI;
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ENDFOR;
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DEST[MAXVL-1:VL] := 0
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</pre>
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<h3 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
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¶
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</a></h3>
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<pre>VALIGND __m512i _mm512_alignr_epi32( __m512i a, __m512i b, int cnt);
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</pre>
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<pre>VALIGND __m512i _mm512_mask_alignr_epi32(__m512i s, __mmask16 k, __m512i a, __m512i b, int cnt);
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</pre>
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<pre>VALIGND __m512i _mm512_maskz_alignr_epi32( __mmask16 k, __m512i a, __m512i b, int cnt);
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</pre>
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<pre>VALIGND __m256i _mm256_mask_alignr_epi32(__m256i s, __mmask8 k, __m256i a, __m256i b, int cnt);
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</pre>
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<pre>VALIGND __m256i _mm256_maskz_alignr_epi32( __mmask8 k, __m256i a, __m256i b, int cnt);
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</pre>
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<pre>VALIGND __m128i _mm_mask_alignr_epi32(__m128i s, __mmask8 k, __m128i a, __m128i b, int cnt);
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</pre>
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<pre>VALIGND __m128i _mm_maskz_alignr_epi32( __mmask8 k, __m128i a, __m128i b, int cnt);
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</pre>
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<pre>VALIGNQ __m512i _mm512_alignr_epi64( __m512i a, __m512i b, int cnt);
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</pre>
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<pre>VALIGNQ __m512i _mm512_mask_alignr_epi64(__m512i s, __mmask8 k, __m512i a, __m512i b, int cnt);
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</pre>
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<pre>VALIGNQ __m512i _mm512_maskz_alignr_epi64( __mmask8 k, __m512i a, __m512i b, int cnt);
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</pre>
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<pre>VALIGNQ __m256i _mm256_mask_alignr_epi64(__m256i s, __mmask8 k, __m256i a, __m256i b, int cnt);
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</pre>
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<pre>VALIGNQ __m256i _mm256_maskz_alignr_epi64( __mmask8 k, __m256i a, __m256i b, int cnt);
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</pre>
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<pre>VALIGNQ __m128i _mm_mask_alignr_epi64(__m128i s, __mmask8 k, __m128i a, __m128i b, int cnt);
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</pre>
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<pre>VALIGNQ __m128i _mm_maskz_alignr_epi64( __mmask8 k, __m128i a, __m128i b, int cnt);
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</pre>
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<h3 class="exceptions" id="exceptions">Exceptions<a class="anchor" href="#exceptions">
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¶
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</a></h3>
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<p>See <span class="not-imported">Table 2-50</span>, “Type E4NF Class Exception Conditions.”</p><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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