forked from NRZCode/ia32-64
82 lines
3.4 KiB
HTML
82 lines
3.4 KiB
HTML
<!DOCTYPE html>
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>UD
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— Undefined Instruction</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>UD
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— Undefined Instruction</h1>
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<table>
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<tr>
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<th>Opcode</th>
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<th>Instruction</th>
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<th>Op/En</th>
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<th>64-Bit Mode</th>
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<th>Compat/Leg Mode</th>
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<th>Description</th></tr>
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<tr>
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<td>0F FF /r</td>
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<td>UD0<sup>1</sup> r32, r/m32</td>
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<td>RM</td>
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<td>Valid</td>
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<td>Valid</td>
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<td>Raise invalid opcode exception.</td></tr>
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<tr>
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<td>0F B9 /r</td>
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<td>UD1 r32, r/m32</td>
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<td>RM</td>
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<td>Valid</td>
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<td>Valid</td>
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<td>Raise invalid opcode exception.</td></tr>
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<tr>
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<td>0F 0B</td>
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<td>UD2</td>
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<td>ZO</td>
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<td>Valid</td>
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<td>Valid</td>
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<td>Raise invalid opcode exception.</td></tr></table>
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<blockquote>
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<p>1. Some processors decode the UD0 instruction without a ModR/M byte. As a result, those processors would deliver an invalid-opcode exception instead of a fault on instruction fetch when the instruction with a ModR/M byte (and any implied bytes) would cross a page or segment boundary.</p></blockquote>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Operand 3</th>
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<th>Operand 4</th></tr>
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<tr>
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<td>ZO</td>
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<td>N/A</td>
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<td>N/A</td>
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<td>N/A</td>
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<td>N/A</td></tr>
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<tr>
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<td>RM</td>
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<td>ModRM:reg (r)</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td>
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<td>N/A</td></tr></table>
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<h2 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h2>
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<p>Generates an invalid opcode exception. This instruction is provided for software testing to explicitly generate an invalid opcode exception. The opcodes for this instruction are reserved for this purpose.</p>
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<p>Other than raising the invalid opcode exception, this instruction has no effect on processor state or memory.</p>
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<p>Even though it is the execution of the UD instruction that causes the invalid opcode exception, the instruction pointer saved by delivery of the exception references the UD instruction (and not the following instruction).</p>
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<p>This instruction’s operation is the same in non-64-bit modes and 64-bit mode.</p>
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<h2 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h2>
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<pre>#UD (* Generates invalid opcode exception *);
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</pre>
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<h2 id="flags-affected">Flags Affected<a class="anchor" href="#flags-affected">
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¶
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</a></h2>
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<p>None.</p>
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<h2 id="exceptions--all-operating-modes-">Exceptions (All Operating Modes)<a class="anchor" href="#exceptions--all-operating-modes-">
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¶
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</a></h2>
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<p>#UD Raises an invalid opcode exception in all operating modes.</p><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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