forked from NRZCode/ia32-64
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HTML
119 lines
6.5 KiB
HTML
<!DOCTYPE html>
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>TPAUSE
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— Timed PAUSE</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>TPAUSE
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— Timed PAUSE</h1>
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<table>
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<tr>
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<th>Opcode / Instruction</th>
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<th>Op/En</th>
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<th>64/32 bit Mode Support</th>
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<th>CPUID Feature Flag</th>
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<th>Description</th></tr>
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<tr>
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<td>66 0F AE /6 TPAUSE r32, <edx>, <eax></td>
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<td>A</td>
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<td>V/V</td>
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<td>WAITPKG</td>
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<td>Directs the processor to enter an implementation-dependent optimized state until the TSC reaches the value in EDX:EAX.</td></tr></table>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<sup>1</sup><a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Tuple</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Operand 3</th>
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<th>Operand 4</th></tr>
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<tr>
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<td>A</td>
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<td>N/A</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td>
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<td>N/A</td>
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<td>N/A</td></tr></table>
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<h2 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h2>
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<p>TPAUSE instructs the processor to enter an implementation-dependent optimized state. There are two such optimized states to choose from: light-weight power/performance optimized state, and improved power/performance optimized state. The selection between the two is governed by the explicit input register bit[0] source operand.</p>
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<p>TPAUSE is available when CPUID.7.0:ECX.WAITPKG[bit 5] is enumerated as 1. TPAUSE may be executed at any privilege level. This instruction’s operation is the same in non-64-bit modes and in 64-bit mode.</p>
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<p>Unlike PAUSE, the TPAUSE instruction will not cause an abort when used inside a transactional region, described in the chapter Chapter 16, “Programming with Intel® Transactional Synchronization Extensions,” of the Intel<sup>®</sup> 64 and IA-32 Architectures Software Developer’s Manual, Volume 1.</p>
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<blockquote>
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<p>1. The Mod field of the ModR/M byte must have value 11B.</p></blockquote>
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<p>The input register contains information such as the preferred optimized state the processor should enter as described in the following table. Bits other than bit 0 are reserved and will result in #GP if non-zero.</p>
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<figure id="tbl-4-20">
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<table>
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<tr>
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<th>Bit Value</th>
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<th>State Name</th>
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<th>Wakeup Time</th>
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<th>Power Savings</th>
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<th>Other Benefits</th></tr>
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<tr>
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<td>bit[0] = 0</td>
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<td>C0.2</td>
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<td>Slower</td>
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<td>Larger</td>
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<td>Improves performance of the other SMT thread(s) on the same core.</td></tr>
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<tr>
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<td>bit[0] = 1</td>
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<td>C0.1</td>
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<td>Faster</td>
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<td>Smaller</td>
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<td>N/A</td></tr>
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<tr>
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<td>bits[31:1]</td>
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<td>N/A</td>
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<td>N/A</td>
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<td>N/A</td>
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<td>Reserved</td></tr></table>
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<figcaption><a href='tpause.html#tbl-4-20'>Table 4-20</a>. TPAUSE Input Register Bit Definitions</figcaption></figure>
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<p>The instruction execution wakes up when the time-stamp counter reaches or exceeds the implicit EDX:EAX 64-bit input value.</p>
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<p>Prior to executing the TPAUSE instruction, an operating system may specify the maximum delay it allows the processor to suspend its operation. It can do so by writing TSC-quanta value to the following 32-bit MSR (IA32_UMWAIT_CONTROL at MSR index E1H):</p>
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<ul>
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<li>IA32_UMWAIT_CONTROL[31:2] — Determines the maximum time in TSC-quanta that the processor can reside in either C0.1 or C0.2. A zero value indicates no maximum time. The maximum time value is a 32-bit value where the upper 30 bits come from this field and the lower two bits are zero.</li>
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<li>IA32_UMWAIT_CONTROL[1] — Reserved.</li>
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<li>IA32_UMWAIT_CONTROL[0] — C0.2 is not allowed by the OS. Value of “1” means all C0.2 requests revert to C0.1.</li></ul>
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<p>If the processor that executed a TPAUSE instruction wakes due to the expiration of the operating system time-limit, the instructions sets RFLAGS.CF; otherwise, that flag is cleared.</p>
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<p>The following additional events cause the processor to exit the implementation-dependent optimized state: a store to the read-set range within the transactional region, an NMI or SMI, a debug exception, a machine check exception, the BINIT# signal, the INIT# signal, and the RESET# signal.</p>
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<p>Other implementation-dependent events may cause the processor to exit the implementation-dependent optimized state proceeding to the instruction following TPAUSE. In addition, an external interrupt causes the processor to exit the implementation-dependent optimized state regardless of whether maskable-interrupts are inhibited (EFLAGS.IF =0). It should be noted that if maskable-interrupts are inhibited execution will proceed to the instruction following TPAUSE.</p>
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<h2 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h2>
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<pre>os_deadline := TSC+(IA32_UMWAIT_CONTROL[31:2]<<2)
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instr_deadline := UINT64(EDX:EAX)
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IF os_deadline < instr_deadline:
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deadline := os_deadline
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using_os_deadline := 1
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ELSE:
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deadline := instr_deadline
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using_os_deadline := 0
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WHILE TSC < deadline:
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implementation_dependent_optimized_state(Source register, deadline, IA32_UMWAIT_CONTROL[0])
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IF using_os_deadline AND TSC ≥ deadline:
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RFLAGS.CF := 1
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ELSE:
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RFLAGS.CF := 0
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RFLAGS.AF,PF,SF,ZF,OF := 0
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</pre>
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<h2 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
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¶
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</a></h2>
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<pre>TPAUSE uint8_t _tpause(uint32_t control, uint64_t counter);
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</pre>
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<h2 class="exceptions" id="numeric-exceptions">Numeric Exceptions<a class="anchor" href="#numeric-exceptions">
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¶
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</a></h2>
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<p>None.</p>
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<h2 id="exceptions--all-operating-modes-">Exceptions (All Operating Modes)<a class="anchor" href="#exceptions--all-operating-modes-">
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¶
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</a></h2>
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<p>#GP(0) If src[31:1] != 0.</p>
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<p>If CR4.TSD = 1 and CPL != 0.</p>
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<p>#UD If CPUID.7.0:ECX.WAITPKG[bit 5]=0.</p><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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