forked from NRZCode/ia32-64
118 lines
5.1 KiB
HTML
118 lines
5.1 KiB
HTML
<!DOCTYPE html>
|
||
<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>STR
|
||
— Store Task Register</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>STR
|
||
— Store Task Register</h1>
|
||
|
||
<table>
|
||
<tr>
|
||
<th>Opcode</th>
|
||
<th>Instruction</th>
|
||
<th>Op/En</th>
|
||
<th>64-Bit Mode</th>
|
||
<th>Compat/Leg Mode</th>
|
||
<th>Description</th></tr>
|
||
<tr>
|
||
<td>0F 00 /1</td>
|
||
<td>STR r/m16</td>
|
||
<td>M</td>
|
||
<td>Valid</td>
|
||
<td>Valid</td>
|
||
<td>Stores segment selector from TR in r/m16.</td></tr></table>
|
||
<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
|
||
¶
|
||
</a></h2>
|
||
<table>
|
||
<tr>
|
||
<th>Op/En</th>
|
||
<th>Operand 1</th>
|
||
<th>Operand 2</th>
|
||
<th>Operand 3</th>
|
||
<th>Operand 4</th></tr>
|
||
<tr>
|
||
<td>M</td>
|
||
<td>ModRM:r/m (w)</td>
|
||
<td>N/A</td>
|
||
<td>N/A</td>
|
||
<td>N/A</td></tr></table>
|
||
<h2 id="description">Description<a class="anchor" href="#description">
|
||
¶
|
||
</a></h2>
|
||
<p>Stores the segment selector from the task register (TR) in the destination operand. The destination operand can be a general-purpose register or a memory location. The segment selector stored with this instruction points to the task state segment (TSS) for the currently running task.</p>
|
||
<p>When the destination operand is a 32-bit register, the 16-bit segment selector is copied into the lower 16 bits of the register and the upper 16 bits of the register are cleared. When the destination operand is a memory location, the segment selector is written to memory as a 16-bit quantity, regardless of operand size.</p>
|
||
<p>In 64-bit mode, operation is the same. The size of the memory operand is fixed at 16 bits. In register stores, the 2-byte TR is zero extended if stored to a 64-bit register.</p>
|
||
<p>The STR instruction is useful only in operating-system software. It can only be executed in protected mode.</p>
|
||
<h2 id="operation">Operation<a class="anchor" href="#operation">
|
||
¶
|
||
</a></h2>
|
||
<pre>DEST := TR(SegmentSelector);
|
||
</pre>
|
||
<h2 id="flags-affected">Flags Affected<a class="anchor" href="#flags-affected">
|
||
¶
|
||
</a></h2>
|
||
<p>None.</p>
|
||
<h2 class="exceptions" id="protected-mode-exceptions">Protected Mode Exceptions<a class="anchor" href="#protected-mode-exceptions">
|
||
¶
|
||
</a></h2>
|
||
<table>
|
||
<tr>
|
||
<td rowspan="3">#GP(0)</td>
|
||
<td>If the destination is a memory operand that is located in a non-writable segment or if the effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
|
||
<tr>
|
||
<td>If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment selector.</td></tr>
|
||
<tr>
|
||
<td>If CR4.UMIP = 1 and CPL > 0.</td></tr>
|
||
<tr>
|
||
<td>#SS(0)</td>
|
||
<td>If a memory operand effective address is outside the SS segment limit.</td></tr>
|
||
<tr>
|
||
<td>#PF(fault-code)</td>
|
||
<td>If a page fault occurs.</td></tr>
|
||
<tr>
|
||
<td>#AC(0)</td>
|
||
<td>If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.</td></tr>
|
||
<tr>
|
||
<td>#UD</td>
|
||
<td>If the LOCK prefix is used.</td></tr></table>
|
||
<h2 class="exceptions" id="real-address-mode-exceptions">Real-Address Mode Exceptions<a class="anchor" href="#real-address-mode-exceptions">
|
||
¶
|
||
</a></h2>
|
||
<table>
|
||
<tr>
|
||
<td>#UD</td>
|
||
<td>The STR instruction is not recognized in real-address mode.</td></tr></table>
|
||
<h2 class="exceptions" id="virtual-8086-mode-exceptions">Virtual-8086 Mode Exceptions<a class="anchor" href="#virtual-8086-mode-exceptions">
|
||
¶
|
||
</a></h2>
|
||
<table>
|
||
<tr>
|
||
<td>#UD</td>
|
||
<td>The STR instruction is not recognized in virtual-8086 mode.</td></tr></table>
|
||
<h2 class="exceptions" id="compatibility-mode-exceptions">Compatibility Mode Exceptions<a class="anchor" href="#compatibility-mode-exceptions">
|
||
¶
|
||
</a></h2>
|
||
<p>Same exceptions as in protected mode.</p>
|
||
<h2 class="exceptions" id="64-bit-mode-exceptions">64-Bit Mode Exceptions<a class="anchor" href="#64-bit-mode-exceptions">
|
||
¶
|
||
</a></h2>
|
||
<table>
|
||
<tr>
|
||
<td rowspan="2">#GP(0)</td>
|
||
<td>If the memory address is in a non-canonical form.</td></tr>
|
||
<tr>
|
||
<td>If CR4.UMIP = 1 and CPL > 0.</td></tr>
|
||
<tr>
|
||
<td>#SS(0)</td>
|
||
<td>If the stack address is in a non-canonical form.</td></tr>
|
||
<tr>
|
||
<td>#PF(fault-code)</td>
|
||
<td>If a page fault occurs.</td></tr>
|
||
<tr>
|
||
<td>#AC(0)</td>
|
||
<td>If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.</td></tr>
|
||
<tr>
|
||
<td>#UD</td>
|
||
<td>If the LOCK prefix is used.</td></tr></table><footer><p>
|
||
This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
|
||
inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
|
||
ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
|
||
</p></footer></body></html>
|