forked from NRZCode/ia32-64
131 lines
6.1 KiB
HTML
131 lines
6.1 KiB
HTML
<!DOCTYPE html>
|
||
<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>SQRTSD
|
||
— Compute Square Root of Scalar Double Precision Floating-Point Value</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>SQRTSD
|
||
— Compute Square Root of Scalar Double Precision Floating-Point Value</h1>
|
||
|
||
<table>
|
||
<tr>
|
||
<th>Opcode/Instruction</th>
|
||
<th>Op / En</th>
|
||
<th>64/32 bit Mode Support</th>
|
||
<th>CPUID Feature Flag</th>
|
||
<th>Description</th></tr>
|
||
<tr>
|
||
<td>F2 0F 51/r SQRTSD xmm1,xmm2/m64</td>
|
||
<td>A</td>
|
||
<td>V/V</td>
|
||
<td>SSE2</td>
|
||
<td>Computes square root of the low double precision floating-point value in xmm2/m64 and stores the results in xmm1.</td></tr>
|
||
<tr>
|
||
<td>VEX.LIG.F2.0F.WIG 51/r VSQRTSD xmm1,xmm2, xmm3/m64</td>
|
||
<td>B</td>
|
||
<td>V/V</td>
|
||
<td>AVX</td>
|
||
<td>Computes square root of the low double precision floating-point value in xmm3/m64 and stores the results in xmm1. Also, upper double precision floating-point value (bits[127:64]) from xmm2 is copied to xmm1[127:64].</td></tr>
|
||
<tr>
|
||
<td>EVEX.LLIG.F2.0F.W1 51/r VSQRTSD xmm1 {k1}{z}, xmm2, xmm3/m64{er}</td>
|
||
<td>C</td>
|
||
<td>V/V</td>
|
||
<td>AVX512F</td>
|
||
<td>Computes square root of the low double precision floating-point value in xmm3/m64 and stores the results in xmm1 under writemask k1. Also, upper double precision floating-point value (bits[127:64]) from xmm2 is copied to xmm1[127:64].</td></tr></table>
|
||
<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
|
||
¶
|
||
</a></h2>
|
||
<table>
|
||
<tr>
|
||
<th>Op/En</th>
|
||
<th>Tuple Type</th>
|
||
<th>Operand 1</th>
|
||
<th>Operand 2</th>
|
||
<th>Operand 3</th>
|
||
<th>Operand 4</th></tr>
|
||
<tr>
|
||
<td>A</td>
|
||
<td>N/A</td>
|
||
<td>ModRM:reg (w)</td>
|
||
<td>ModRM:r/m (r)</td>
|
||
<td>N/A</td>
|
||
<td>N/A</td></tr>
|
||
<tr>
|
||
<td>B</td>
|
||
<td>N/A</td>
|
||
<td>ModRM:reg (w)</td>
|
||
<td>VEX.vvvv (r)</td>
|
||
<td>ModRM:r/m (r)</td>
|
||
<td>N/A</td></tr>
|
||
<tr>
|
||
<td>C</td>
|
||
<td>Tuple1 Scalar</td>
|
||
<td>ModRM:reg (w)</td>
|
||
<td>EVEX.vvvv (r)</td>
|
||
<td>ModRM:r/m (r)</td>
|
||
<td>N/A</td></tr></table>
|
||
<h2 id="description">Description<a class="anchor" href="#description">
|
||
¶
|
||
</a></h2>
|
||
<p>Computes the square root of the low double precision floating-point value in the second source operand and stores the double precision floating-point result in the destination operand. The second source operand can be an XMM register or a 64-bit memory location. The first source and destination operands are XMM registers.</p>
|
||
<p>128-bit Legacy SSE version: The first source operand and the destination operand are the same. The quadword at bits 127:64 of the destination operand remains unchanged. Bits (MAXVL-1:64) of the corresponding destination register remain unchanged.</p>
|
||
<p>VEX.128 and EVEX encoded versions: Bits 127:64 of the destination operand are copied from the corresponding bits of the first source operand. Bits (MAXVL-1:128) of the destination register are zeroed.</p>
|
||
<p>EVEX encoded version: The low quadword element of the destination operand is updated according to the write-mask.</p>
|
||
<p>Software should ensure VSQRTSD is encoded with VEX.L=0. Encoding VSQRTSD with VEX.L=1 may encounter unpredictable behavior across different processor generations.</p>
|
||
<h2 id="operation">Operation<a class="anchor" href="#operation">
|
||
¶
|
||
</a></h2>
|
||
<h3 id="vsqrtsd--evex-encoded-version-">VSQRTSD (EVEX Encoded Version)<a class="anchor" href="#vsqrtsd--evex-encoded-version-">
|
||
¶
|
||
</a></h3>
|
||
<pre>IF (EVEX.b = 1) AND (SRC2 *is register*)
|
||
THEN
|
||
SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(EVEX.RC);
|
||
ELSE
|
||
SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(MXCSR.RC);
|
||
FI;
|
||
IF k1[0] or *no writemask*
|
||
THEN DEST[63:0] := SQRT(SRC2[63:0])
|
||
ELSE
|
||
IF *merging-masking* ; merging-masking
|
||
THEN *DEST[63:0] remains unchanged*
|
||
ELSE ; zeroing-masking
|
||
THEN DEST[63:0] := 0
|
||
FI;
|
||
FI;
|
||
DEST[127:64] := SRC1[127:64]
|
||
DEST[MAXVL-1:128] := 0
|
||
</pre>
|
||
<h3 id="vsqrtsd--vex-128-encoded-version-">VSQRTSD (VEX.128 Encoded Version)<a class="anchor" href="#vsqrtsd--vex-128-encoded-version-">
|
||
¶
|
||
</a></h3>
|
||
<pre>DEST[63:0] := SQRT(SRC2[63:0])
|
||
DEST[127:64] := SRC1[127:64]
|
||
DEST[MAXVL-1:128] := 0
|
||
</pre>
|
||
<h3 id="sqrtsd--128-bit-legacy-sse-version-">SQRTSD (128-bit Legacy SSE Version)<a class="anchor" href="#sqrtsd--128-bit-legacy-sse-version-">
|
||
¶
|
||
</a></h3>
|
||
<pre>DEST[63:0] := SQRT(SRC[63:0])
|
||
DEST[MAXVL-1:64] (Unmodified)
|
||
</pre>
|
||
<h2 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
|
||
¶
|
||
</a></h2>
|
||
<pre>VSQRTSD __m128d _mm_sqrt_round_sd(__m128d a, __m128d b, int r);
|
||
</pre>
|
||
<pre>VSQRTSD __m128d _mm_mask_sqrt_round_sd(__m128d s, __mmask8 k, __m128d a, __m128d b, int r);
|
||
</pre>
|
||
<pre>VSQRTSD __m128d _mm_maskz_sqrt_round_sd(__mmask8 k, __m128d a, __m128d b, int r);
|
||
</pre>
|
||
<pre>SQRTSD __m128d _mm_sqrt_sd (__m128d a, __m128d b)
|
||
</pre>
|
||
<h2 class="exceptions" id="simd-floating-point-exceptions">SIMD Floating-Point Exceptions<a class="anchor" href="#simd-floating-point-exceptions">
|
||
¶
|
||
</a></h2>
|
||
<p>Invalid, Precision, Denormal.</p>
|
||
<h2 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
|
||
¶
|
||
</a></h2>
|
||
<p>Non-EVEX-encoded instruction, see <span class="not-imported">Table 2-20</span>, “Type 3 Class Exception Conditions.”</p>
|
||
<p>EVEX-encoded instruction, see <span class="not-imported">Table 2-47</span>, “Type E3 Class Exception Conditions.”</p><footer><p>
|
||
This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
|
||
inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
|
||
ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
|
||
</p></footer></body></html>
|