forked from NRZCode/ia32-64
178 lines
8 KiB
HTML
178 lines
8 KiB
HTML
<!DOCTYPE html>
|
||
<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>SQRTPD
|
||
— Square Root of Double Precision Floating-Point Values</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>SQRTPD
|
||
— Square Root of Double Precision Floating-Point Values</h1>
|
||
|
||
<table>
|
||
<tr>
|
||
<th>Opcode/Instruction</th>
|
||
<th>Op / En</th>
|
||
<th>64/32 bit Mode Support</th>
|
||
<th>CPUID Feature Flag</th>
|
||
<th>Description</th></tr>
|
||
<tr>
|
||
<td>66 0F 51 /r SQRTPD xmm1, xmm2/m128</td>
|
||
<td>A</td>
|
||
<td>V/V</td>
|
||
<td>SSE2</td>
|
||
<td>Computes Square Roots of the packed double precision floating-point values in xmm2/m128 and stores the result in xmm1.</td></tr>
|
||
<tr>
|
||
<td>VEX.128.66.0F.WIG 51 /r VSQRTPD xmm1, xmm2/m128</td>
|
||
<td>A</td>
|
||
<td>V/V</td>
|
||
<td>AVX</td>
|
||
<td>Computes Square Roots of the packed double precision floating-point values in xmm2/m128 and stores the result in xmm1.</td></tr>
|
||
<tr>
|
||
<td>VEX.256.66.0F.WIG 51 /r VSQRTPD ymm1, ymm2/m256</td>
|
||
<td>A</td>
|
||
<td>V/V</td>
|
||
<td>AVX</td>
|
||
<td>Computes Square Roots of the packed double precision floating-point values in ymm2/m256 and stores the result in ymm1.</td></tr>
|
||
<tr>
|
||
<td>EVEX.128.66.0F.W1 51 /r VSQRTPD xmm1 {k1}{z}, xmm2/m128/m64bcst</td>
|
||
<td>B</td>
|
||
<td>V/V</td>
|
||
<td>AVX512VL AVX512F</td>
|
||
<td>Computes Square Roots of the packed double precision floating-point values in xmm2/m128/m64bcst and stores the result in xmm1 subject to writemask k1.</td></tr>
|
||
<tr>
|
||
<td>EVEX.256.66.0F.W1 51 /r VSQRTPD ymm1 {k1}{z}, ymm2/m256/m64bcst</td>
|
||
<td>B</td>
|
||
<td>V/V</td>
|
||
<td>AVX512VL AVX512F</td>
|
||
<td>Computes Square Roots of the packed double precision floating-point values in ymm2/m256/m64bcst and stores the result in ymm1 subject to writemask k1.</td></tr>
|
||
<tr>
|
||
<td>EVEX.512.66.0F.W1 51 /r VSQRTPD zmm1 {k1}{z}, zmm2/m512/m64bcst{er}</td>
|
||
<td>B</td>
|
||
<td>V/V</td>
|
||
<td>AVX512F</td>
|
||
<td>Computes Square Roots of the packed double precision floating-point values in zmm2/m512/m64bcst and stores the result in zmm1 subject to writemask k1.</td></tr></table>
|
||
<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
|
||
¶
|
||
</a></h2>
|
||
<table>
|
||
<tr>
|
||
<th>Op/En</th>
|
||
<th>Tuple Type</th>
|
||
<th>Operand 1</th>
|
||
<th>Operand 2</th>
|
||
<th>Operand 3</th>
|
||
<th>Operand 4</th></tr>
|
||
<tr>
|
||
<td>A</td>
|
||
<td>N/A</td>
|
||
<td>ModRM:reg (w)</td>
|
||
<td>ModRM:r/m (r)</td>
|
||
<td>N/A</td>
|
||
<td>N/A</td></tr>
|
||
<tr>
|
||
<td>B</td>
|
||
<td>Full</td>
|
||
<td>ModRM:reg (w)</td>
|
||
<td>ModRM:r/m (r)</td>
|
||
<td>N/A</td>
|
||
<td>N/A</td></tr></table>
|
||
<h2 id="description">Description<a class="anchor" href="#description">
|
||
¶
|
||
</a></h2>
|
||
<p>Performs a SIMD computation of the square roots of the two, four or eight packed double precision floating-point values in the source operand (the second operand) stores the packed double precision floating-point results in the destination operand (the first operand).</p>
|
||
<p>EVEX encoded versions: The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from a 64-bit memory location. The destination operand is a ZMM/YMM/XMM register updated according to the writemask.</p>
|
||
<p>VEX.256 encoded version: The source operand is a YMM register or a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAXVL-1:256) of the corresponding ZMM register destination are zeroed.</p>
|
||
<p>VEX.128 encoded version: the source operand second source operand or a 128-bit memory location. The destination operand is an XMM register. The upper bits (MAXVL-1:128) of the corresponding ZMM register destination are zeroed.</p>
|
||
<p>128-bit Legacy SSE version: The second source can be an XMM register or 128-bit memory location. The destination is not distinct from the first source XMM register and the upper bits (MAXVL-1:128) of the corresponding ZMM register destination are unmodified.</p>
|
||
<p>Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.</p>
|
||
<h2 id="operation">Operation<a class="anchor" href="#operation">
|
||
¶
|
||
</a></h2>
|
||
<h3 id="vsqrtpd--evex-encoded-versions-">VSQRTPD (EVEX Encoded Versions)<a class="anchor" href="#vsqrtpd--evex-encoded-versions-">
|
||
¶
|
||
</a></h3>
|
||
<pre>(KL, VL) = (2, 128), (4, 256), (8, 512)
|
||
IF (VL = 512) AND (EVEX.b = 1) AND (SRC *is register*)
|
||
THEN
|
||
SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(EVEX.RC);
|
||
ELSE
|
||
SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(MXCSR.RC);
|
||
FI;
|
||
FOR j := 0 TO KL-1
|
||
i := j * 64
|
||
IF k1[j] OR *no writemask* THEN
|
||
IF (EVEX.b = 1) AND (SRC *is memory*)
|
||
THEN DEST[i+63:i] := SQRT(SRC[63:0])
|
||
ELSE DEST[i+63:i] := SQRT(SRC[i+63:i])
|
||
FI;
|
||
ELSE
|
||
IF *merging-masking* ; merging-masking
|
||
THEN *DEST[i+63:i] remains unchanged*
|
||
ELSE ; zeroing-masking
|
||
DEST[i+63:i] := 0
|
||
FI
|
||
FI;
|
||
ENDFOR
|
||
DEST[MAXVL-1:VL] := 0
|
||
</pre>
|
||
<h3 id="vsqrtpd--vex-256-encoded-version-">VSQRTPD (VEX.256 Encoded Version)<a class="anchor" href="#vsqrtpd--vex-256-encoded-version-">
|
||
¶
|
||
</a></h3>
|
||
<pre>DEST[63:0] := SQRT(SRC[63:0])
|
||
DEST[127:64] := SQRT(SRC[127:64])
|
||
DEST[191:128] := SQRT(SRC[191:128])
|
||
DEST[255:192] := SQRT(SRC[255:192])
|
||
DEST[MAXVL-1:256] := 0
|
||
.
|
||
</pre>
|
||
<h3 id="vsqrtpd--vex-128-encoded-version-">VSQRTPD (VEX.128 Encoded Version)<a class="anchor" href="#vsqrtpd--vex-128-encoded-version-">
|
||
¶
|
||
</a></h3>
|
||
<pre>DEST[63:0] := SQRT(SRC[63:0])
|
||
DEST[127:64] := SQRT(SRC[127:64])
|
||
DEST[MAXVL-1:128] := 0
|
||
</pre>
|
||
<h3 id="sqrtpd--128-bit-legacy-sse-version-">SQRTPD (128-bit Legacy SSE Version)<a class="anchor" href="#sqrtpd--128-bit-legacy-sse-version-">
|
||
¶
|
||
</a></h3>
|
||
<pre>DEST[63:0] := SQRT(SRC[63:0])
|
||
DEST[127:64] := SQRT(SRC[127:64])
|
||
DEST[MAXVL-1:128] (Unmodified)
|
||
</pre>
|
||
<h2 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
|
||
¶
|
||
</a></h2>
|
||
<pre>VSQRTPD __m512d _mm512_sqrt_round_pd(__m512d a, int r);
|
||
</pre>
|
||
<pre>VSQRTPD __m512d _mm512_mask_sqrt_round_pd(__m512d s, __mmask8 k, __m512d a, int r);
|
||
</pre>
|
||
<pre>VSQRTPD __m512d _mm512_maskz_sqrt_round_pd( __mmask8 k, __m512d a, int r);
|
||
</pre>
|
||
<pre>VSQRTPD __m256d _mm256_sqrt_pd (__m256d a);
|
||
</pre>
|
||
<pre>VSQRTPD __m256d _mm256_mask_sqrt_pd(__m256d s, __mmask8 k, __m256d a, int r);
|
||
</pre>
|
||
<pre>VSQRTPD __m256d _mm256_maskz_sqrt_pd( __mmask8 k, __m256d a, int r);
|
||
</pre>
|
||
<pre>SQRTPD __m128d _mm_sqrt_pd (__m128d a);
|
||
</pre>
|
||
<pre>VSQRTPD __m128d _mm_mask_sqrt_pd(__m128d s, __mmask8 k, __m128d a, int r);
|
||
</pre>
|
||
<pre>VSQRTPD __m128d _mm_maskz_sqrt_pd( __mmask8 k, __m128d a, int r);
|
||
</pre>
|
||
<h2 class="exceptions" id="simd-floating-point-exceptions">SIMD Floating-Point Exceptions<a class="anchor" href="#simd-floating-point-exceptions">
|
||
¶
|
||
</a></h2>
|
||
<p>Invalid, Precision, Denormal.</p>
|
||
<h2 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
|
||
¶
|
||
</a></h2>
|
||
<p>Non-EVEX-encoded instruction, see <span class="not-imported">Table 2-19</span>, “Type 2 Class Exception Conditions,” additionally:</p>
|
||
<table>
|
||
<tr>
|
||
<td>#UD</td>
|
||
<td>If VEX.vvvv != 1111B.</td></tr></table>
|
||
<p>EVEX-encoded instruction, see <span class="not-imported">Table 2-46</span>, “Type E2 Class Exception Conditions,” additionally:</p>
|
||
<table>
|
||
<tr>
|
||
<td>#UD</td>
|
||
<td>If EVEX.vvvv != 1111B.</td></tr></table><footer><p>
|
||
This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
|
||
inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
|
||
ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
|
||
</p></footer></body></html>
|