forked from NRZCode/ia32-64
74 lines
3.3 KiB
HTML
74 lines
3.3 KiB
HTML
<!DOCTYPE html>
|
||
<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>SHA256MSG2
|
||
— Perform a Final Calculation for the Next Four SHA256 Message Dwords</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>SHA256MSG2
|
||
— Perform a Final Calculation for the Next Four SHA256 Message Dwords</h1>
|
||
|
||
<table>
|
||
<tr>
|
||
<th>Opcode/Instruction</th>
|
||
<th>Op/En</th>
|
||
<th>64/32 bit Mode Support</th>
|
||
<th>CPUID Feature Flag</th>
|
||
<th>Description</th></tr>
|
||
<tr>
|
||
<td>NP 0F 38 CD /r SHA256MSG2 xmm1, xmm2/m128</td>
|
||
<td>RM</td>
|
||
<td>V/V</td>
|
||
<td>SHA</td>
|
||
<td>Performs the final calculation for the next four SHA256 message dwords using previous message dwords from xmm1 and xmm2/m128, storing the result in xmm1.</td></tr></table>
|
||
<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
|
||
¶
|
||
</a></h2>
|
||
<table>
|
||
<tr>
|
||
<th>Op/En</th>
|
||
<th>Operand 1</th>
|
||
<th>Operand 2</th>
|
||
<th>Operand 3</th></tr>
|
||
<tr>
|
||
<td>RM</td>
|
||
<td>ModRM:reg (r, w)</td>
|
||
<td>ModRM:r/m (r)</td>
|
||
<td>N/A</td></tr></table>
|
||
<h2 id="description">Description<a class="anchor" href="#description">
|
||
¶
|
||
</a></h2>
|
||
<p>The SHA256MSG2 instruction is one of two SHA2 message scheduling instructions. The instruction performs the final calculation for the next four SHA256 message dwords.</p>
|
||
<h2 id="operation">Operation<a class="anchor" href="#operation">
|
||
¶
|
||
</a></h2>
|
||
<h3 id="sha256msg2">SHA256MSG2<a class="anchor" href="#sha256msg2">
|
||
¶
|
||
</a></h3>
|
||
<pre>W14 := SRC2[95:64] ;
|
||
W15 := SRC2[127:96] ;
|
||
W16 := SRC1[31: 0] + σ<sub>1</sub>( W14) ;
|
||
W17 := SRC1[63: 32] + σ<sub>1</sub>( W15) ;
|
||
W18 := SRC1[95: 64] + σ<sub>1</sub>( W16) ;
|
||
W19 := SRC1[127: 96] + σ<sub>1</sub>( W17) ;
|
||
DEST[127:96] := W19 ;
|
||
DEST[95:64] := W18 ;
|
||
DEST[63:32] := W17 ;
|
||
DEST[31:0] := W16;
|
||
</pre>
|
||
<h2 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
|
||
¶
|
||
</a></h2>
|
||
<pre>SHA256MSG2 __m128i _mm_sha256msg2_epu32(__m128i, __m128i);
|
||
</pre>
|
||
<h2 id="flags-affected">Flags Affected<a class="anchor" href="#flags-affected">
|
||
¶
|
||
</a></h2>
|
||
<p>None.</p>
|
||
<h2 class="exceptions" id="simd-floating-point-exceptions">SIMD Floating-Point Exceptions<a class="anchor" href="#simd-floating-point-exceptions">
|
||
¶
|
||
</a></h2>
|
||
<p>None.</p>
|
||
<h2 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
|
||
¶
|
||
</a></h2>
|
||
<p>See <span class="not-imported">Table 2-21</span>, “Type 4 Class Exception Conditions.”</p><footer><p>
|
||
This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
|
||
inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
|
||
ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
|
||
</p></footer></body></html>
|