forked from NRZCode/ia32-64
104 lines
5.7 KiB
HTML
104 lines
5.7 KiB
HTML
<!DOCTYPE html>
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>RDTSC
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— Read Time-Stamp Counter</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>RDTSC
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— Read Time-Stamp Counter</h1>
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<table>
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<tr>
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<th>Opcode*</th>
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<th>Instruction</th>
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<th>Op/En</th>
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<th>64-Bit Mode</th>
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<th>Compat/Leg Mode</th>
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<th>Description</th></tr>
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<tr>
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<td>0F 31</td>
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<td>RDTSC</td>
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<td>ZO</td>
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<td>Valid</td>
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<td>Valid</td>
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<td>Read time-stamp counter into EDX:EAX.</td></tr></table>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Operand 3</th>
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<th>Operand 4</th></tr>
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<tr>
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<td>ZO</td>
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<td>N/A</td>
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<td>N/A</td>
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<td>N/A</td>
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<td>N/A</td></tr></table>
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<h2 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h2>
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<p>Reads the current value of the processor’s time-stamp counter (a 64-bit MSR) into the EDX:EAX registers. The EDX register is loaded with the high-order 32 bits of the MSR and the EAX register is loaded with the low-order 32 bits. (On processors that support the Intel 64 architecture, the high-order 32 bits of each of RAX and RDX are cleared.)</p>
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<p>The processor monotonically increments the time-stamp counter MSR every clock cycle and resets it to 0 whenever the processor is reset. See “Time Stamp Counter” in Chapter 18 of the Intel<sup>®</sup> 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B, for specific details of the time stamp counter behavior.</p>
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<p>The time stamp disable (TSD) flag in register CR4 restricts the use of the RDTSC instruction as follows. When the flag is clear, the RDTSC instruction can be executed at any privilege level; when the flag is set, the instruction can only be executed at privilege level 0.</p>
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<p>The time-stamp counter can also be read with the RDMSR instruction, when executing at privilege level 0.</p>
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<p>The RDTSC instruction is not a serializing instruction. It does not necessarily wait until all previous instructions have been executed before reading the counter. Similarly, subsequent instructions may begin execution before the read operation is performed. The following items may guide software seeking to order executions of RDTSC:</p>
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<ul>
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<li>If software requires RDTSC to be executed only after all previous instructions have executed and all previous loads are globally visible,<sup>1 </sup>it can execute LFENCE immediately before RDTSC.</li>
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<li>If software requires RDTSC to be executed only after all previous instructions have executed and all previous loads and stores are globally visible, it can execute the sequence MFENCE;LFENCE immediately before RDTSC.</li>
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<li>If software requires RDTSC to be executed prior to execution of any subsequent instruction (including any memory accesses), it can execute the sequence LFENCE immediately after RDTSC.</li></ul>
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<p>This instruction was introduced by the Pentium processor.</p>
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<p>See “Changes to Instruction Behavior in VMX Non-Root Operation” in Chapter 26 of the Intel<sup>®</sup> 64 and IA-32 Architectures Software Developer’s Manual, Volume 3C, for more information about the behavior of this instruction in VMX non-root operation.</p>
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<blockquote>
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<p>1. A load is considered to become globally visible when the value to be loaded is determined.</p></blockquote>
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<h2 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h2>
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<pre>IF (CR4.TSD = 0) or (CPL = 0) or (CR0.PE = 0)
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THEN EDX:EAX := TimeStampCounter;
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ELSE (* CR4.TSD = 1 and (CPL = 1, 2, or 3) and CR0.PE = 1 *)
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#GP(0);
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FI;
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</pre>
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<h2 id="flags-affected">Flags Affected<a class="anchor" href="#flags-affected">
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¶
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</a></h2>
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<p>None.</p>
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<h2 class="exceptions" id="protected-mode-exceptions">Protected Mode Exceptions<a class="anchor" href="#protected-mode-exceptions">
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¶
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</a></h2>
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<table>
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<tr>
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<td>#GP(0)</td>
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<td>If the TSD flag in register CR4 is set and the CPL is greater than 0.</td></tr>
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<tr>
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<td>#UD</td>
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<td>If the LOCK prefix is used.</td></tr></table>
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<h2 class="exceptions" id="real-address-mode-exceptions">Real-Address Mode Exceptions<a class="anchor" href="#real-address-mode-exceptions">
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¶
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</a></h2>
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<table>
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<tr>
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<td>#UD</td>
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<td>If the LOCK prefix is used.</td></tr></table>
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<h2 class="exceptions" id="virtual-8086-mode-exceptions">Virtual-8086 Mode Exceptions<a class="anchor" href="#virtual-8086-mode-exceptions">
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¶
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</a></h2>
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<table>
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<tr>
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<td>#GP(0)</td>
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<td>If the TSD flag in register CR4 is set.</td></tr>
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<tr>
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<td>#UD</td>
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<td>If the LOCK prefix is used.</td></tr></table>
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<h2 class="exceptions" id="compatibility-mode-exceptions">Compatibility Mode Exceptions<a class="anchor" href="#compatibility-mode-exceptions">
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¶
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</a></h2>
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<p>Same exceptions as in protected mode.</p>
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<h2 class="exceptions" id="64-bit-mode-exceptions">64-Bit Mode Exceptions<a class="anchor" href="#64-bit-mode-exceptions">
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¶
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</a></h2>
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<p>Same exceptions as in protected mode.</p><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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