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141 lines
5.9 KiB
HTML
<!DOCTYPE html>
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>PUSHA/PUSHAD
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— Push All General-Purpose Registers</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>PUSHA/PUSHAD
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— Push All General-Purpose Registers</h1>
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<table>
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<tr>
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<th>Opcode</th>
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<th>Instruction</th>
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<th>Op/En</th>
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<th>64-Bit Mode</th>
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<th>Compat/Leg Mode</th>
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<th>Description</th></tr>
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<tr>
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<td>60</td>
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<td>PUSHA</td>
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<td>ZO</td>
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<td>Invalid</td>
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<td>Valid</td>
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<td>Push AX, CX, DX, BX, original SP, BP, SI, and DI.</td></tr>
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<tr>
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<td>60</td>
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<td>PUSHAD</td>
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<td>ZO</td>
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<td>Invalid</td>
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<td>Valid</td>
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<td>Push EAX, ECX, EDX, EBX, original ESP, EBP, ESI, and EDI.</td></tr></table>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Operand 3</th>
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<th>Operand 4</th></tr>
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<tr>
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<td>ZO</td>
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<td>N/A</td>
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<td>N/A</td>
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<td>N/A</td>
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<td>N/A</td></tr></table>
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<h2 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h2>
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<p>Pushes the contents of the general-purpose registers onto the stack. The registers are stored on the stack in the following order: EAX, ECX, EDX, EBX, ESP (original value), EBP, ESI, and EDI (if the current operand-size attribute is 32) and AX, CX, DX, BX, SP (original value), BP, SI, and DI (if the operand-size attribute is 16). These instructions perform the reverse operation of the POPA/POPAD instructions. The value pushed for the ESP or SP register is its value before prior to pushing the first register (see the “Operation” section below).</p>
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<p>The PUSHA (push all) and PUSHAD (push all double) mnemonics reference the same opcode. The PUSHA instruction is intended for use when the operand-size attribute is 16 and the PUSHAD instruction for when the operand-size attribute is 32. Some assemblers may force the operand size to 16 when PUSHA is used and to 32 when PUSHAD is used. Others may treat these mnemonics as synonyms (PUSHA/PUSHAD) and use the current setting of the operand-size attribute to determine the size of values to be pushed from the stack, regardless of the mnemonic used.</p>
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<p>In the real-address mode, if the ESP or SP register is 1, 3, or 5 when PUSHA/PUSHAD executes: an #SS exception is generated but not delivered (the stack error reported prevents #SS delivery). Next, the processor generates a #DF exception and enters a shutdown state as described in the #DF discussion in Chapter 6 of the Intel<sup>®</sup> 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.</p>
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<p>This instruction executes as described in compatibility mode and legacy mode. It is not valid in 64-bit mode.</p>
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<h2 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h2>
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<pre>IF 64-bit Mode
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THEN #UD
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FI;
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IF OperandSize = 32 (* PUSHAD instruction *)
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THEN
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Temp := (ESP);
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Push(EAX);
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Push(ECX);
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Push(EDX);
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Push(EBX);
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Push(Temp);
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Push(EBP);
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Push(ESI);
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Push(EDI);
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ELSE (* OperandSize = 16, PUSHA instruction *)
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Temp := (SP);
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Push(AX);
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Push(CX);
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Push(DX);
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Push(BX);
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Push(Temp);
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Push(BP);
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Push(SI);
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Push(DI);
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FI;
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</pre>
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<h2 id="flags-affected">Flags Affected<a class="anchor" href="#flags-affected">
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¶
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</a></h2>
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<p>None.</p>
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<h2 class="exceptions" id="protected-mode-exceptions">Protected Mode Exceptions<a class="anchor" href="#protected-mode-exceptions">
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¶
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</a></h2>
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<table>
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<tr>
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<td>#SS(0)</td>
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<td>If the starting or ending stack address is outside the stack segment limit.</td></tr>
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<tr>
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<td>#PF(fault-code)</td>
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<td>If a page fault occurs.</td></tr>
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<tr>
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<td>#AC(0)</td>
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<td>If an unaligned memory reference is made while the current privilege level is 3 and alignment checking is enabled.</td></tr>
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<tr>
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<td>#UD</td>
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<td>If the LOCK prefix is used.</td></tr></table>
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<h2 class="exceptions" id="real-address-mode-exceptions">Real-Address Mode Exceptions<a class="anchor" href="#real-address-mode-exceptions">
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¶
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</a></h2>
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<table>
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<tr>
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<td>#GP</td>
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<td>If the ESP or SP register contains 7, 9, 11, 13, or 15.</td></tr>
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<tr>
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<td>#UD</td>
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<td>If the LOCK prefix is used.</td></tr></table>
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<h2 class="exceptions" id="virtual-8086-mode-exceptions">Virtual-8086 Mode Exceptions<a class="anchor" href="#virtual-8086-mode-exceptions">
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¶
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</a></h2>
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<table>
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<tr>
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<td>#GP(0)</td>
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<td>If the ESP or SP register contains 7, 9, 11, 13, or 15.</td></tr>
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<tr>
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<td>#PF(fault-code)</td>
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<td>If a page fault occurs.</td></tr>
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<tr>
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<td>#AC(0)</td>
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<td>If an unaligned memory reference is made while alignment checking is enabled.</td></tr>
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<tr>
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<td>#UD</td>
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<td>If the LOCK prefix is used.</td></tr></table>
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<h2 class="exceptions" id="compatibility-mode-exceptions">Compatibility Mode Exceptions<a class="anchor" href="#compatibility-mode-exceptions">
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¶
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</a></h2>
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<p>Same exceptions as in protected mode.</p>
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<h2 class="exceptions" id="64-bit-mode-exceptions">64-Bit Mode Exceptions<a class="anchor" href="#64-bit-mode-exceptions">
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¶
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</a></h2>
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<table>
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<tr>
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<td>#UD</td>
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<td>If in 64-bit mode.</td></tr></table><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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