forked from NRZCode/ia32-64
824 lines
44 KiB
HTML
824 lines
44 KiB
HTML
<!DOCTYPE html>
|
||
<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>PSRAW/PSRAD/PSRAQ
|
||
— Shift Packed Data Right Arithmetic</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>PSRAW/PSRAD/PSRAQ
|
||
— Shift Packed Data Right Arithmetic</h1>
|
||
|
||
|
||
|
||
<table>
|
||
<tr>
|
||
<th>Opcode/Instruction</th>
|
||
<th>Op/En</th>
|
||
<th>64/32 bit Mode Support</th>
|
||
<th>CPUID Feature Flag</th>
|
||
<th>Description</th></tr>
|
||
<tr>
|
||
<td>NP 0F E1 /r<sup>1</sup> PSRAW mm, mm/m64</td>
|
||
<td>A</td>
|
||
<td>V/V</td>
|
||
<td>MMX</td>
|
||
<td>Shift words in mm right by mm/m64 while shifting in sign bits.</td></tr>
|
||
<tr>
|
||
<td>66 0F E1 /r PSRAW xmm1, xmm2/m128</td>
|
||
<td>A</td>
|
||
<td>V/V</td>
|
||
<td>SSE2</td>
|
||
<td>Shift words in xmm1 right by xmm2/m128 while shifting in sign bits.</td></tr>
|
||
<tr>
|
||
<td>NP 0F 71 /4 ib<sup>1</sup> PSRAW mm, imm8</td>
|
||
<td>B</td>
|
||
<td>V/V</td>
|
||
<td>MMX</td>
|
||
<td>Shift words in mm right by imm8 while shifting in sign bits</td></tr>
|
||
<tr>
|
||
<td>66 0F 71 /4 ib PSRAW xmm1, imm8</td>
|
||
<td>B</td>
|
||
<td>V/V</td>
|
||
<td>SSE2</td>
|
||
<td>Shift words in xmm1 right by imm8 while shifting in sign bits</td></tr>
|
||
<tr>
|
||
<td>NP 0F E2 /r<sup>1</sup> PSRAD mm, mm/m64</td>
|
||
<td>A</td>
|
||
<td>V/V</td>
|
||
<td>MMX</td>
|
||
<td>Shift doublewords in mm right by mm/m64 while shifting in sign bits.</td></tr>
|
||
<tr>
|
||
<td>66 0F E2 /r PSRAD xmm1, xmm2/m128</td>
|
||
<td>A</td>
|
||
<td>V/V</td>
|
||
<td>SSE2</td>
|
||
<td>Shift doubleword in xmm1 right by xmm2 /m128 while shifting in sign bits.</td></tr>
|
||
<tr>
|
||
<td>NP 0F 72 /4 ib<sup>1</sup> PSRAD mm, imm8</td>
|
||
<td>B</td>
|
||
<td>V/V</td>
|
||
<td>MMX</td>
|
||
<td>Shift doublewords in mm right by imm8 while shifting in sign bits.</td></tr>
|
||
<tr>
|
||
<td>66 0F 72 /4 ib PSRAD xmm1, imm8</td>
|
||
<td>B</td>
|
||
<td>V/V</td>
|
||
<td>SSE2</td>
|
||
<td>Shift doublewords in xmm1 right by imm8 while shifting in sign bits.</td></tr>
|
||
<tr>
|
||
<td>VEX.128.66.0F.WIG E1 /r VPSRAW xmm1, xmm2, xmm3/m128</td>
|
||
<td>C</td>
|
||
<td>V/V</td>
|
||
<td>AVX</td>
|
||
<td>Shift words in xmm2 right by amount specified in xmm3/m128 while shifting in sign bits.</td></tr>
|
||
<tr>
|
||
<td>VEX.128.66.0F.WIG 71 /4 ib VPSRAW xmm1, xmm2, imm8</td>
|
||
<td>D</td>
|
||
<td>V/V</td>
|
||
<td>AVX</td>
|
||
<td>Shift words in xmm2 right by imm8 while shifting in sign bits.</td></tr>
|
||
<tr>
|
||
<td>VEX.128.66.0F.WIG E2 /r VPSRAD xmm1, xmm2, xmm3/m128</td>
|
||
<td>C</td>
|
||
<td>V/V</td>
|
||
<td>AVX</td>
|
||
<td>Shift doublewords in xmm2 right by amount specified in xmm3/m128 while shifting in sign bits.</td></tr>
|
||
<tr>
|
||
<td>VEX.128.66.0F.WIG 72 /4 ib VPSRAD xmm1, xmm2, imm8</td>
|
||
<td>D</td>
|
||
<td>V/V</td>
|
||
<td>AVX</td>
|
||
<td>Shift doublewords in xmm2 right by imm8 while shifting in sign bits.</td></tr>
|
||
<tr>
|
||
<td>VEX.256.66.0F.WIG E1 /r VPSRAW ymm1, ymm2, xmm3/m128</td>
|
||
<td>C</td>
|
||
<td>V/V</td>
|
||
<td>AVX2</td>
|
||
<td>Shift words in ymm2 right by amount specified in xmm3/m128 while shifting in sign bits.</td></tr>
|
||
<tr>
|
||
<td>VEX.256.66.0F.WIG 71 /4 ib VPSRAW ymm1, ymm2, imm8</td>
|
||
<td>D</td>
|
||
<td>V/V</td>
|
||
<td>AVX2</td>
|
||
<td>Shift words in ymm2 right by imm8 while shifting in sign bits.</td></tr>
|
||
<tr>
|
||
<td>VEX.256.66.0F.WIG E2 /r VPSRAD ymm1, ymm2, xmm3/m128</td>
|
||
<td>C</td>
|
||
<td>V/V</td>
|
||
<td>AVX2</td>
|
||
<td>Shift doublewords in ymm2 right by amount specified in xmm3/m128 while shifting in sign bits.</td></tr>
|
||
<tr>
|
||
<td>VEX.256.66.0F.WIG 72 /4 ib VPSRAD ymm1, ymm2, imm8</td>
|
||
<td>D</td>
|
||
<td>V/V</td>
|
||
<td>AVX2</td>
|
||
<td>Shift doublewords in ymm2 right by imm8 while shifting in sign bits.</td></tr>
|
||
<tr>
|
||
<td>EVEX.128.66.0F.WIG E1 /r VPSRAW xmm1 {k1}{z}, xmm2, xmm3/m128</td>
|
||
<td>G</td>
|
||
<td>V/V</td>
|
||
<td>AVX512VL AVX512BW</td>
|
||
<td>Shift words in xmm2 right by amount specified in xmm3/m128 while shifting in sign bits using writemask k1.</td></tr>
|
||
<tr>
|
||
<td>EVEX.256.66.0F.WIG E1 /r VPSRAW ymm1 {k1}{z}, ymm2, xmm3/m128</td>
|
||
<td>G</td>
|
||
<td>V/V</td>
|
||
<td>AVX512VL AVX512BW</td>
|
||
<td>Shift words in ymm2 right by amount specified in xmm3/m128 while shifting in sign bits using writemask k1.</td></tr>
|
||
<tr>
|
||
<td>EVEX.512.66.0F.WIG E1 /r VPSRAW zmm1 {k1}{z}, zmm2, xmm3/m128</td>
|
||
<td>G</td>
|
||
<td>V/V</td>
|
||
<td>AVX512BW</td>
|
||
<td>Shift words in zmm2 right by amount specified in xmm3/m128 while shifting in sign bits using writemask k1.</td></tr>
|
||
<tr>
|
||
<td>EVEX.128.66.0F.WIG 71 /4 ib VPSRAW xmm1 {k1}{z}, xmm2/m128, imm8</td>
|
||
<td>E</td>
|
||
<td>V/V</td>
|
||
<td>AVX512VL AVX512BW</td>
|
||
<td>Shift words in xmm2/m128 right by imm8 while shifting in sign bits using writemask k1.</td></tr>
|
||
<tr>
|
||
<td>EVEX.256.66.0F.WIG 71 /4 ib VPSRAW ymm1 {k1}{z}, ymm2/m256, imm8</td>
|
||
<td>E</td>
|
||
<td>V/V</td>
|
||
<td>AVX512VL AVX512BW</td>
|
||
<td>Shift words in ymm2/m256 right by imm8 while shifting in sign bits using writemask k1.</td></tr>
|
||
<tr>
|
||
<td>EVEX.512.66.0F.WIG 71 /4 ib VPSRAW zmm1 {k1}{z}, zmm2/m512, imm8</td>
|
||
<td>E</td>
|
||
<td>V/V</td>
|
||
<td>AVX512BW</td>
|
||
<td>Shift words in zmm2/m512 right by imm8 while shifting in sign bits using writemask k1.</td></tr>
|
||
<tr>
|
||
<td>EVEX.128.66.0F.W0 E2 /r VPSRAD xmm1 {k1}{z}, xmm2, xmm3/m128</td>
|
||
<td>G</td>
|
||
<td>V/V</td>
|
||
<td>AVX512VL AVX512F</td>
|
||
<td>Shift doublewords in xmm2 right by amount specified in xmm3/m128 while shifting in sign bits using writemask k1.</td></tr>
|
||
<tr>
|
||
<td>EVEX.256.66.0F.W0 E2 /r VPSRAD ymm1 {k1}{z}, ymm2, xmm3/m128</td>
|
||
<td>G</td>
|
||
<td>V/V</td>
|
||
<td>AVX512VL AVX512F</td>
|
||
<td>Shift doublewords in ymm2 right by amount specified in xmm3/m128 while shifting in sign bits using writemask k1.</td></tr>
|
||
<tr>
|
||
<td>EVEX.512.66.0F.W0 E2 /r VPSRAD zmm1 {k1}{z}, zmm2, xmm3/m128</td>
|
||
<td>G</td>
|
||
<td>V/V</td>
|
||
<td>AVX512F</td>
|
||
<td>Shift doublewords in zmm2 right by amount specified in xmm3/m128 while shifting in sign bits using writemask k1.</td></tr>
|
||
<tr>
|
||
<td>EVEX.128.66.0F.W0 72 /4 ib VPSRAD xmm1 {k1}{z}, xmm2/m128/m32bcst, imm8</td>
|
||
<td>F</td>
|
||
<td>V/V</td>
|
||
<td>AVX512VL AVX512F</td>
|
||
<td>Shift doublewords in xmm2/m128/m32bcst right by imm8 while shifting in sign bits using writemask k1.</td></tr>
|
||
<tr>
|
||
<td>EVEX.256.66.0F.W0 72 /4 ib VPSRAD ymm1 {k1}{z}, ymm2/m256/m32bcst, imm8</td>
|
||
<td>F</td>
|
||
<td>V/V</td>
|
||
<td>AVX512VL AVX512F</td>
|
||
<td>Shift doublewords in ymm2/m256/m32bcst right by imm8 while shifting in sign bits using writemask k1.</td></tr>
|
||
<tr>
|
||
<td>EVEX.512.66.0F.W0 72 /4 ib VPSRAD zmm1 {k1}{z}, zmm2/m512/m32bcst, imm8</td>
|
||
<td>F</td>
|
||
<td>V/V</td>
|
||
<td>AVX512F</td>
|
||
<td>Shift doublewords in zmm2/m512/m32bcst right by imm8 while shifting in sign bits using writemask k1.</td></tr>
|
||
<tr>
|
||
<td>EVEX.128.66.0F.W1 E2 /r VPSRAQ xmm1 {k1}{z}, xmm2, xmm3/m128</td>
|
||
<td>G</td>
|
||
<td>V/V</td>
|
||
<td>AVX512VL AVX512F</td>
|
||
<td>Shift quadwords in xmm2 right by amount specified in xmm3/m128 while shifting in sign bits using writemask k1.</td></tr>
|
||
<tr>
|
||
<td>EVEX.256.66.0F.W1 E2 /r VPSRAQ ymm1 {k1}{z}, ymm2, xmm3/m128</td>
|
||
<td>G</td>
|
||
<td>V/V</td>
|
||
<td>AVX512VL AVX512F</td>
|
||
<td>Shift quadwords in ymm2 right by amount specified in xmm3/m128 while shifting in sign bits using writemask k1.</td></tr>
|
||
<tr>
|
||
<td>EVEX.512.66.0F.W1 E2 /r VPSRAQ zmm1 {k1}{z}, zmm2, xmm3/m128</td>
|
||
<td>G</td>
|
||
<td>V/V</td>
|
||
<td>AVX512F</td>
|
||
<td>Shift quadwords in zmm2 right by amount specified in xmm3/m128 while shifting in sign bits using writemask k1.</td></tr>
|
||
<tr>
|
||
<td>EVEX.128.66.0F.W1 72 /4 ib VPSRAQ xmm1 {k1}{z}, xmm2/m128/m64bcst, imm8</td>
|
||
<td>F</td>
|
||
<td>V/V</td>
|
||
<td>AVX512VL AVX512F</td>
|
||
<td>Shift quadwords in xmm2/m128/m64bcst right by imm8 while shifting in sign bits using writemask k1.</td></tr>
|
||
<tr>
|
||
<td>EVEX.256.66.0F.W1 72 /4 ib VPSRAQ ymm1 {k1}{z}, ymm2/m256/m64bcst, imm8</td>
|
||
<td>F</td>
|
||
<td>V/V</td>
|
||
<td>AVX512VL AVX512F</td>
|
||
<td>Shift quadwords in ymm2/m256/m64bcst right by imm8 while shifting in sign bits using writemask k1.</td></tr>
|
||
<tr>
|
||
<td>EVEX.512.66.0F.W1 72 /4 ib VPSRAQ zmm1 {k1}{z}, zmm2/m512/m64bcst, imm8</td>
|
||
<td>F</td>
|
||
<td>V/V</td>
|
||
<td>AVX512F</td>
|
||
<td>Shift quadwords in zmm2/m512/m64bcst right by imm8 while shifting in sign bits using writemask k1.</td></tr></table>
|
||
<blockquote>
|
||
<p>1. See note in Section 2.5, “Intel® AVX and Intel® SSE Instruction Exception Classification,” in the Intel<sup>®</sup> 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A, and Section 23.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers,” in the Intel<sup>®</sup> 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.</p></blockquote>
|
||
<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
|
||
¶
|
||
</a></h2>
|
||
<table>
|
||
<tr>
|
||
<th>Op/En</th>
|
||
<th>Tuple Type</th>
|
||
<th>Operand 1</th>
|
||
<th>Operand 2</th>
|
||
<th>Operand 3</th>
|
||
<th>Operand 4</th></tr>
|
||
<tr>
|
||
<td>A</td>
|
||
<td>N/A</td>
|
||
<td>ModRM:reg (r, w)</td>
|
||
<td>ModRM:r/m (r)</td>
|
||
<td>N/A</td>
|
||
<td>N/A</td></tr>
|
||
<tr>
|
||
<td>B</td>
|
||
<td>N/A</td>
|
||
<td>ModRM:r/m (r, w)</td>
|
||
<td>imm8</td>
|
||
<td>N/A</td>
|
||
<td>N/A</td></tr>
|
||
<tr>
|
||
<td>C</td>
|
||
<td>N/A</td>
|
||
<td>ModRM:reg (w)</td>
|
||
<td>VEX.vvvv (r)</td>
|
||
<td>ModRM:r/m (r)</td>
|
||
<td>N/A</td></tr>
|
||
<tr>
|
||
<td>D</td>
|
||
<td>N/A</td>
|
||
<td>VEX.vvvv (w)</td>
|
||
<td>ModRM:r/m (r)</td>
|
||
<td>imm8</td>
|
||
<td>N/A</td></tr>
|
||
<tr>
|
||
<td>E</td>
|
||
<td>Full Mem</td>
|
||
<td>EVEX.vvvv (w)</td>
|
||
<td>ModRM:r/m (r)</td>
|
||
<td>imm8</td>
|
||
<td>N/A</td></tr>
|
||
<tr>
|
||
<td>F</td>
|
||
<td>Full</td>
|
||
<td>EVEX.vvvv (w)</td>
|
||
<td>ModRM:r/m (r)</td>
|
||
<td>imm8</td>
|
||
<td>N/A</td></tr>
|
||
<tr>
|
||
<td>G</td>
|
||
<td>Mem128</td>
|
||
<td>ModRM:reg (w)</td>
|
||
<td>EVEX.vvvv (r)</td>
|
||
<td>ModRM:r/m (r)</td>
|
||
<td>N/A</td></tr></table>
|
||
<h2 id="description">Description<a class="anchor" href="#description">
|
||
¶
|
||
</a></h2>
|
||
<p>Shifts the bits in the individual data elements (words, doublewords or quadwords) in the destination operand (first operand) to the right by the number of bits specified in the count operand (second operand). As the bits in the data elements are shifted right, the empty high-order bits are filled with the initial value of the sign bit of the data element. If the value specified by the count operand is greater than 15 (for words), 31 (for doublewords), or 63 (for quadwords), each destination data element is filled with the initial value of the sign bit of the element. (<a href='psraw.psrad.psraq.html#fig-4-18'>Figure 4-18</a> gives an example of shifting words in a 64-bit operand.)</p>
|
||
<figure id="fig-4-18">
|
||
<svg style="width: 455.616pt; height: 126.287976pt" viewBox="109.64 0.0 384.68 110.23998">
|
||
<g xmlns="http://www.w3.org/2000/svg" style="fill: none; stroke: none">
|
||
<rect height="104.28" style="fill: rgb(0%, 0%, 0%)" width="0.48" x="112.14" y="0.47998000000001184"></rect>
|
||
<rect height="104.28" style="fill: rgb(0%, 0%, 0%)" width="0.47998" x="491.34000000000003" y="0.47998000000001184"></rect>
|
||
<rect height="0.47998" style="fill: rgb(0%, 0%, 0%)" width="379.68" x="112.14" y="0.0"></rect>
|
||
<rect height="0.48001000000000005" style="fill: rgb(0%, 0%, 0%)" width="379.68" x="112.14" y="104.75997000000001"></rect>
|
||
<rect height="0.48001000000000005" style="fill: rgb(0%, 0%, 0%)" width="63.120000000000005" x="194.70000000000002" y="11.159969999999987"></rect>
|
||
<rect height="18.240000000000002" style="fill: rgb(0%, 0%, 0%)" width="0.48001000000000005" x="257.34000000000003" y="11.399979999999971"></rect>
|
||
<rect height="0.48001000000000005" style="fill: rgb(0%, 0%, 0%)" width="63.120000000000005" x="194.46" y="29.159969999999987"></rect>
|
||
<rect height="18.240000000000002" style="fill: rgb(0%, 0%, 0%)" width="0.47998" x="194.46" y="11.159979999999962"></rect>
|
||
<rect height="18.0" style="fill: rgb(100%, 100%, 100%)" width="62.88" x="257.58" y="11.399979999999971"></rect>
|
||
<rect height="0.48001000000000005" style="fill: rgb(0%, 0%, 0%)" width="63.120000000000005" x="257.58" y="11.159969999999987"></rect>
|
||
<rect height="18.240000000000002" style="fill: rgb(0%, 0%, 0%)" width="0.48001000000000005" x="320.22" y="11.399979999999971"></rect>
|
||
<rect height="0.48001000000000005" style="fill: rgb(0%, 0%, 0%)" width="63.120000000000005" x="257.34000000000003" y="29.159969999999987"></rect>
|
||
<rect height="18.240000000000002" style="fill: rgb(0%, 0%, 0%)" width="0.48001000000000005" x="257.34000000000003" y="11.159979999999962"></rect>
|
||
<rect height="18.0" style="fill: rgb(100%, 100%, 100%)" width="62.940000000000005" x="320.46" y="11.399979999999971"></rect>
|
||
<rect height="0.48001000000000005" style="fill: rgb(0%, 0%, 0%)" width="63.18" x="320.46" y="11.159969999999987"></rect>
|
||
<rect height="18.240000000000002" style="fill: rgb(0%, 0%, 0%)" width="0.48001000000000005" x="383.16" y="11.399979999999971"></rect>
|
||
<rect height="0.48001000000000005" style="fill: rgb(0%, 0%, 0%)" width="63.18" x="320.22" y="29.159969999999987"></rect>
|
||
<rect height="18.240000000000002" style="fill: rgb(0%, 0%, 0%)" width="0.48001000000000005" x="320.22" y="11.159979999999962"></rect>
|
||
<rect height="18.0" style="fill: rgb(100%, 100%, 100%)" width="62.88" x="383.40000000000003" y="11.399979999999971"></rect>
|
||
<rect height="0.48001000000000005" style="fill: rgb(0%, 0%, 0%)" width="63.120000000000005" x="383.40000000000003" y="11.159969999999987"></rect>
|
||
<rect height="18.240000000000002" style="fill: rgb(0%, 0%, 0%)" width="0.47998" x="446.04" y="11.399979999999971"></rect>
|
||
<rect height="0.48001000000000005" style="fill: rgb(0%, 0%, 0%)" width="63.120000000000005" x="383.16" y="29.159969999999987"></rect>
|
||
<rect height="18.240000000000002" style="fill: rgb(0%, 0%, 0%)" width="0.48001000000000005" x="383.16" y="11.159979999999962"></rect>
|
||
<rect height="18.0" style="fill: rgb(100%, 100%, 100%)" width="62.940000000000005" x="194.10000000000002" y="64.37997999999999"></rect>
|
||
<rect height="0.48001000000000005" style="fill: rgb(0%, 0%, 0%)" width="63.18" x="194.10000000000002" y="64.13997"></rect>
|
||
<rect height="18.240000000000002" style="fill: rgb(0%, 0%, 0%)" width="0.48001000000000005" x="256.8" y="64.37997999999999"></rect>
|
||
<rect height="0.48001000000000005" style="fill: rgb(0%, 0%, 0%)" width="63.18" x="193.86" y="82.13997"></rect>
|
||
<rect height="18.240000000000002" style="fill: rgb(0%, 0%, 0%)" width="0.48" x="193.86" y="64.13997999999998"></rect>
|
||
<rect height="18.0" style="fill: rgb(100%, 100%, 100%)" width="62.88" x="257.04" y="64.37997999999999"></rect>
|
||
<rect height="0.48001000000000005" style="fill: rgb(0%, 0%, 0%)" width="63.120000000000005" x="257.04" y="64.13997"></rect>
|
||
<rect height="18.240000000000002" style="fill: rgb(0%, 0%, 0%)" width="0.48001000000000005" x="319.68" y="64.37997999999999"></rect>
|
||
<rect height="0.48001000000000005" style="fill: rgb(0%, 0%, 0%)" width="63.120000000000005" x="256.8" y="82.13997"></rect>
|
||
<rect height="18.240000000000002" style="fill: rgb(0%, 0%, 0%)" width="0.48001000000000005" x="256.8" y="64.13997999999998"></rect>
|
||
<rect height="18.0" style="fill: rgb(100%, 100%, 100%)" width="62.88" x="319.92" y="64.37997999999999"></rect>
|
||
<rect height="0.48001000000000005" style="fill: rgb(0%, 0%, 0%)" width="63.120000000000005" x="319.92" y="64.13997"></rect>
|
||
<rect height="18.240000000000002" style="fill: rgb(0%, 0%, 0%)" width="0.48001000000000005" x="382.56" y="64.37997999999999"></rect>
|
||
<rect height="0.48001000000000005" style="fill: rgb(0%, 0%, 0%)" width="63.120000000000005" x="319.68" y="82.13997"></rect>
|
||
<rect height="18.240000000000002" style="fill: rgb(0%, 0%, 0%)" width="0.48001000000000005" x="319.68" y="64.13997999999998"></rect>
|
||
<rect height="18.0" style="fill: rgb(100%, 100%, 100%)" width="62.88" x="382.8" y="64.37997999999999"></rect>
|
||
<rect height="0.48001000000000005" style="fill: rgb(0%, 0%, 0%)" width="63.120000000000005" x="382.8" y="64.13997"></rect>
|
||
<rect height="18.240000000000002" style="fill: rgb(0%, 0%, 0%)" width="0.48001000000000005" x="445.44" y="64.37997999999999"></rect>
|
||
<rect height="0.48001000000000005" style="fill: rgb(0%, 0%, 0%)" width="63.120000000000005" x="382.56" y="82.13997"></rect>
|
||
<rect height="18.240000000000002" style="fill: rgb(0%, 0%, 0%)" width="0.48001000000000005" x="382.56" y="64.13997999999998"></rect>
|
||
<rect height="1.02" style="fill: rgb(0%, 0%, 0%)" width="0.47998" x="420.54" y="56.999979999999994"></rect>
|
||
<path d="M 420.6 57.53997999999996 L 422.16 56.99997999999994 L 423.12 56.63997999999998 L 422.82000000000005 57.65997999999996 L 421.26000000000005 63.05997999999994 L 420.78000000000003 64.73997999999995 L 420.3 63.05997999999994 L 418.74 57.65997999999996 L 418.44 56.63997999999998 L 419.40000000000003 56.99997999999994 L 419.70000000000005 57.35997999999995 L 421.26000000000005 62.759979999999985 L 420.3 63.05997999999994 L 420.3 62.759979999999985 L 421.86 57.35997999999995 L 422.82000000000005 57.65997999999996 L 422.52000000000004 57.95997999999997 L 420.96000000000004 58.49997999999994" style="fill: rgb(0%, 0%, 0%); fill-rule: nonzero"></path>
|
||
<path d="M 419.40000000000003 56.999979999999994 L 420.96000000000004 57.539980000000014 L 420.96000000000004 58.499979999999994 L 420.78000000000003 58.559979999999996 L 420.6 58.499979999999994 L 419.04 57.95997999999997" style="fill: rgb(0%, 0%, 0%); fill-rule: nonzero"></path>
|
||
<path d="M 420.78000000000003 58.019979999999975 L 422.34000000000003 57.479979999999955 L 420.78000000000003 62.87997999999999 L 419.22 57.479979999999955" style="fill: rgb(0%, 0%, 0%); fill-rule: evenodd"></path>
|
||
<rect height="15.0" style="fill: rgb(0%, 0%, 0%)" width="0.47998" x="394.8" y="29.579979999999978"></rect>
|
||
<rect height="0.48001000000000005" style="fill: rgb(0%, 0%, 0%)" width="25.98" x="395.04" y="44.099969999999985"></rect>
|
||
<rect height="12.9" style="fill: rgb(0%, 0%, 0%)" width="0.47998" x="420.54" y="44.339980000000025"></rect>
|
||
<rect height="1.08" style="fill: rgb(0%, 0%, 0%)" width="0.48001000000000005" x="238.38" y="56.93997999999999"></rect>
|
||
<path d="M 238.44 57.53997999999996 L 239.94 56.939979999999935 L 240.9 56.519979999999975 L 239.1 62.99997999999994 L 238.62 64.67997999999994 L 238.14 62.99997999999994 L 236.57999999999998 57.59997999999996 L 236.28 56.57997999999998 L 237.24 56.939979999999935 L 237.54 57.29997999999995 L 239.1 62.69997999999998 L 238.14 62.99997999999994 L 238.14 62.69997999999998 L 239.64 57.29997999999995 L 240.6 57.59997999999996 L 240.3 57.89997999999997 L 238.8 58.49997999999994" style="fill: rgb(0%, 0%, 0%); fill-rule: nonzero"></path>
|
||
<path d="M 237.24 56.93997999999999 L 238.8 57.539980000000014 L 238.8 58.499979999999994 L 238.62 58.559979999999996 L 238.44 58.499979999999994 L 236.88 57.89997999999997" style="fill: rgb(0%, 0%, 0%); fill-rule: nonzero"></path>
|
||
<path d="M 238.62 58.019979999999975 L 240.12 57.41997999999995 L 238.62 62.81997999999999 L 237.06 57.41997999999995" style="fill: rgb(0%, 0%, 0%); fill-rule: evenodd"></path>
|
||
<rect height="14.94" style="fill: rgb(0%, 0%, 0%)" width="0.48" x="212.64000000000001" y="29.579979999999978"></rect>
|
||
<rect height="0.48001000000000005" style="fill: rgb(0%, 0%, 0%)" width="25.98" x="212.88" y="44.03996999999998"></rect>
|
||
<rect height="12.9" style="fill: rgb(0%, 0%, 0%)" width="0.48001000000000005" x="238.38" y="44.27998000000002"></rect>
|
||
<rect height="1.08" style="fill: rgb(0%, 0%, 0%)" width="0.47998" x="302.1" y="56.87997999999999"></rect>
|
||
<path d="M 302.16 57.47998000000001 L 303.66 56.93997999999999 L 304.62 56.51998000000003 L 304.32000000000005 57.599980000000016 L 302.82000000000005 62.93997999999999 L 302.34000000000003 64.55998 L 301.86 62.93997999999999 L 300.3 57.599980000000016 L 300.0 56.579980000000035 L 300.96000000000004 56.93997999999999 L 301.26000000000005 57.299980000000005 L 302.82000000000005 62.63998000000004 L 301.86 62.93997999999999 L 301.86 62.63998000000004 L 303.36 57.299980000000005 L 304.32000000000005 57.599980000000016 L 304.02000000000004 57.89998000000003 L 302.52000000000004 58.43997999999999" style="fill: rgb(0%, 0%, 0%); fill-rule: nonzero"></path>
|
||
<path d="M 300.96 56.93997999999999 L 302.52 57.47998000000001 L 302.52 58.43997999999999 L 302.34 58.499979999999994 L 302.15999999999997 58.43997999999999 L 300.59999999999997 57.89997999999997" style="fill: rgb(0%, 0%, 0%); fill-rule: nonzero"></path>
|
||
<path d="M 302.34000000000003 57.95997999999997 L 303.84000000000003 57.41997999999995 L 302.34000000000003 62.759979999999985 L 300.78000000000003 57.41997999999995" style="fill: rgb(0%, 0%, 0%); fill-rule: evenodd"></path>
|
||
<rect height="14.94" style="fill: rgb(0%, 0%, 0%)" width="0.47998" x="276.36" y="29.519979999999975"></rect>
|
||
<rect height="0.48001000000000005" style="fill: rgb(0%, 0%, 0%)" width="25.98" x="276.6" y="43.97996999999998"></rect>
|
||
<rect height="12.9" style="fill: rgb(0%, 0%, 0%)" width="0.47998" x="302.1" y="44.21998000000002"></rect>
|
||
<rect height="1.02" style="fill: rgb(0%, 0%, 0%)" width="0.47998" x="358.8" y="57.41998000000001"></rect>
|
||
<path d="M 358.86 57.95997999999997 L 360.42 57.41997999999995 L 361.38 57.059979999999996 L 361.08000000000004 58.07997999999998 L 359.52000000000004 63.479979999999955 L 359.04 65.21997999999996 L 358.56 63.479979999999955 L 357.06 58.07997999999998 L 356.76 57.059979999999996 L 357.72 57.41997999999995 L 358.02000000000004 57.779979999999966 L 359.52000000000004 63.17998 L 358.56 63.479979999999955 L 358.56 63.17998 L 360.12 57.779979999999966 L 361.08000000000004 58.07997999999998 L 360.78000000000003 58.37997999999999 L 359.22 58.91997999999995" style="fill: rgb(0%, 0%, 0%); fill-rule: nonzero"></path>
|
||
<path d="M 357.72 57.41998000000001 L 359.22 57.95998000000003 L 359.22 58.91998000000001 L 359.04 58.97998000000001 L 358.86 58.91998000000001 L 357.36 58.37997999999999" style="fill: rgb(0%, 0%, 0%); fill-rule: nonzero"></path>
|
||
<path d="M 359.04 58.43997999999999 L 360.6 57.89997999999997 L 359.04 63.299980000000005 L 357.54 57.89997999999997" style="fill: rgb(0%, 0%, 0%); fill-rule: evenodd"></path>
|
||
<rect height="14.94" style="fill: rgb(0%, 0%, 0%)" width="0.48001000000000005" x="333.12" y="30.059979999999996"></rect>
|
||
<rect height="0.48001000000000005" style="fill: rgb(0%, 0%, 0%)" width="25.92" x="333.36" y="44.51997"></rect>
|
||
<rect height="12.9" style="fill: rgb(0%, 0%, 0%)" width="0.47998" x="358.8" y="44.75998000000004"></rect>
|
||
<text lengthAdjust="spacingAndGlyphs" style="font-size: 8.917956000000004pt; fill: #000" textLength="31.14172609999997" x="160.07982600000003" y="21.185806799999966">Pre-Shift</text>
|
||
<text lengthAdjust="spacingAndGlyphs" style="font-size: 8.917956000000004pt; fill: #000" textLength="9.783381300000002" x="220.9211901" y="25.266628499999968">X3</text>
|
||
<text lengthAdjust="spacingAndGlyphs" style="font-size: 8.917956000000004pt; fill: #000" textLength="9.783381299999974" x="284.6398259" y="25.266628499999968">X2</text>
|
||
<text lengthAdjust="spacingAndGlyphs" style="font-size: 8.917956000000004pt; fill: #000" textLength="9.783381299999974" x="345.65910189999994" y="25.266628499999968">X1</text>
|
||
<text lengthAdjust="spacingAndGlyphs" style="font-size: 8.917956000000004pt; fill: #000" textLength="9.722649699999977" x="407.94" y="25.266080999999986">X0</text>
|
||
<text lengthAdjust="spacingAndGlyphs" style="font-size: 8.917956000000004pt; fill: #000" textLength="21.32638079999998" x="170.58" y="29.466080999999974">DEST</text>
|
||
<text lengthAdjust="spacingAndGlyphs" style="font-size: 8.720880000000022pt; fill: #000" textLength="31.534368000000057" x="159.0" y="42.60334">Shift Right</text>
|
||
<text lengthAdjust="spacingAndGlyphs" style="font-size: 8.720880000000022pt; fill: #000" textLength="27.52819200000002" x="163.02" y="49.863339999999994">with Sign</text>
|
||
<text lengthAdjust="spacingAndGlyphs" style="font-size: 8.720880000000022pt; fill: #000" textLength="29.38164000000006" x="161.160288" y="57.663411999999994">Extension</text>
|
||
<text lengthAdjust="spacingAndGlyphs" style="font-size: 8.917956000000004pt; fill: #000" textLength="34.60902100000007" x="155.21969980000003" y="74.04547269999995">Post-Shift</text>
|
||
<text lengthAdjust="spacingAndGlyphs" style="font-size: 8.918503499999986pt; fill: #000" textLength="53.6597218" x="386.5201245" y="79.02608099999998">X0 >> COUNT</text>
|
||
<text lengthAdjust="spacingAndGlyphs" style="font-size: 8.917956000000004pt; fill: #000" textLength="53.65973149999999" x="198.9001148" y="79.02608099999998">X3 >> COUNT</text>
|
||
<text lengthAdjust="spacingAndGlyphs" style="font-size: 8.917956000000004pt; fill: #000" textLength="53.61479029999998" x="262.6803064" y="79.02608099999998">X2 >> COUNT</text>
|
||
<text lengthAdjust="spacingAndGlyphs" style="font-size: 8.917956000000004pt; fill: #000" textLength="53.59618460000007" x="325.9205328" y="79.02608099999998">X1 >> COUNT</text>
|
||
<text lengthAdjust="spacingAndGlyphs" style="font-size: 8.917956000000004pt; fill: #000" textLength="21.32078709999996" x="169.56" y="82.02608099999998">DEST</text></g></svg>
|
||
<figcaption><a href='psraw.psrad.psraq.html#fig-4-18'>Figure 4-18</a>. PSRAW and PSRAD Instruction Operation Using a 64-bit Operand</figcaption></figure>
|
||
<p>Note that only the first 64-bits of a 128-bit count operand are checked to compute the count. If the second source operand is a memory address, 128 bits are loaded.</p>
|
||
<p>The (V)PSRAW instruction shifts each of the words in the destination operand to the right by the number of bits specified in the count operand, and the (V)PSRAD instruction shifts each of the doublewords in the destination operand.</p>
|
||
<p>In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to access additional registers (XMM8-XMM15).</p>
|
||
<p>Legacy SSE instructions 64-bit operand: The destination operand is an MMX technology register; the count operand can be either an MMX technology register or an 64-bit memory location.</p>
|
||
<p>128-bit Legacy SSE version: The destination and first source operands are XMM registers. Bits (MAXVL-1:128) of the corresponding YMM destination register remain unchanged. The count operand can be either an XMM register or a 128-bit memory location or an 8-bit immediate. If the count operand is a memory address, 128 bits are loaded but the upper 64 bits are ignored.</p>
|
||
<p>VEX.128 encoded version: The destination and first source operands are XMM registers. Bits (MAXVL-1:128) of the destination YMM register are zeroed. The count operand can be either an XMM register or a 128-bit memory location or an 8-bit immediate. If the count operand is a memory address, 128 bits are loaded but the upper 64 bits are ignored.</p>
|
||
<p>VEX.256 encoded version: The destination operand is a YMM register. The source operand is a YMM register or a memory location. The count operand can come either from an XMM register or a memory location or an 8-bit immediate. Bits (MAXVL-1:256) of the corresponding ZMM register are zeroed.</p>
|
||
<p>EVEX encoded versions: The destination operand is a ZMM register updated according to the writemask. The count operand is either an 8-bit immediate (the immediate count version) or an 8-bit value from an XMM register or a memory location (the variable count version). For the immediate count version, the source operand (the second operand) can be a ZMM register, a 512-bit memory location or a 512-bit vector broadcasted from a 32/64-bit memory location. For the variable count version, the first source operand (the second operand) is a ZMM register, the second source operand (the third operand, 8-bit variable count) can be an XMM register or a memory location.</p>
|
||
<p>Note: In VEX/EVEX encoded versions of shifts with an immediate count, vvvv of VEX/EVEX encode the destination register, and VEX.B/EVEX.B + ModRM.r/m encodes the source register.</p>
|
||
<p>Note: For shifts with an immediate count (VEX.128.66.0F 71-73 /4, EVEX.128.66.0F 71-73 /4), VEX.vvvv/EVEX.vvvv encodes the destination register.</p>
|
||
<h2 id="operation">Operation<a class="anchor" href="#operation">
|
||
¶
|
||
</a></h2>
|
||
<h3 id="psraw--with-64-bit-operand-">PSRAW (With 64-bit Operand)<a class="anchor" href="#psraw--with-64-bit-operand-">
|
||
¶
|
||
</a></h3>
|
||
<pre> IF (COUNT > 15)
|
||
THEN COUNT := 16;
|
||
FI;
|
||
DEST[15:0] := SignExtend(DEST[15:0] >> COUNT);
|
||
(* Repeat shift operation for 2nd and 3rd words *)
|
||
DEST[63:48] := SignExtend(DEST[63:48] >> COUNT);
|
||
PSRAD (with 64-bit operand)
|
||
IF (COUNT > 31)
|
||
THEN COUNT := 32;
|
||
FI;
|
||
DEST[31:0] := SignExtend(DEST[31:0] >> COUNT);
|
||
DEST[63:32] := SignExtend(DEST[63:32] >> COUNT);
|
||
ARITHMETIC_RIGHT_SHIFT_DWORDS1(SRC, COUNT_SRC)
|
||
COUNT := COUNT_SRC[63:0];
|
||
IF (COUNT > 31)
|
||
THEN
|
||
DEST[31:0] := SignBit
|
||
ELSE
|
||
DEST[31:0] := SignExtend(SRC[31:0] >> COUNT);
|
||
FI;
|
||
ARITHMETIC_RIGHT_SHIFT_QWORDS1(SRC, COUNT_SRC)
|
||
COUNT := COUNT_SRC[63:0];
|
||
IF (COUNT > 63)
|
||
THEN
|
||
DEST[63:0] := SignBit
|
||
ELSE
|
||
DEST[63:0] := SignExtend(SRC[63:0] >> COUNT);
|
||
FI;
|
||
ARITHMETIC_RIGHT_SHIFT_WORDS_256b(SRC, COUNT_SRC)
|
||
COUNT := COUNT_SRC[63:0];
|
||
IF (COUNT > 15)
|
||
THEN COUNT := 16;
|
||
FI;
|
||
DEST[15:0] := SignExtend(SRC[15:0] >> COUNT);
|
||
(* Repeat shift operation for 2nd through 15th words *)
|
||
DEST[255:240] := SignExtend(SRC[255:240] >> COUNT);
|
||
ARITHMETIC_RIGHT_SHIFT_DWORDS_256b(SRC, COUNT_SRC)
|
||
COUNT := COUNT_SRC[63:0];
|
||
IF (COUNT > 31)
|
||
THEN COUNT := 32;
|
||
FI;
|
||
DEST[31:0] := SignExtend(SRC[31:0] >> COUNT);
|
||
(* Repeat shift operation for 2nd through 7th words *)
|
||
DEST[255:224] := SignExtend(SRC[255:224] >> COUNT);
|
||
ARITHMETIC_RIGHT_SHIFT_QWORDS(SRC, COUNT_SRC, VL) ; VL: 128b, 256b or 512b
|
||
COUNT := COUNT_SRC[63:0];
|
||
IF (COUNT > 63)
|
||
THEN COUNT := 64;
|
||
FI;
|
||
DEST[63:0] := SignExtend(SRC[63:0] >> COUNT);
|
||
(* Repeat shift operation for 2nd through 7th words *)
|
||
DEST[VL-1:VL-64] := SignExtend(SRC[VL-1:VL-64] >> COUNT);
|
||
ARITHMETIC_RIGHT_SHIFT_WORDS(SRC, COUNT_SRC)
|
||
COUNT := COUNT_SRC[63:0];
|
||
IF (COUNT > 15)
|
||
THEN COUNT := 16;
|
||
FI;
|
||
DEST[15:0] := SignExtend(SRC[15:0] >> COUNT);
|
||
(* Repeat shift operation for 2nd through 7th words *)
|
||
DEST[127:112] := SignExtend(SRC[127:112] >> COUNT);
|
||
ARITHMETIC_RIGHT_SHIFT_DWORDS(SRC, COUNT_SRC)
|
||
COUNT := COUNT_SRC[63:0];
|
||
IF (COUNT > 31)
|
||
THEN COUNT := 32;
|
||
FI;
|
||
DEST[31:0] := SignExtend(SRC[31:0] >> COUNT);
|
||
(* Repeat shift operation for 2nd through 3rd words *)
|
||
DEST[127:96] := SignExtend(SRC[127:96] >> COUNT);
|
||
</pre>
|
||
<h3 id="vpsraw--evex-versions--xmm-m128-">VPSRAW (EVEX versions, xmm/m128)<a class="anchor" href="#vpsraw--evex-versions--xmm-m128-">
|
||
¶
|
||
</a></h3>
|
||
<pre>(KL, VL) = (8, 128), (16, 256), (32, 512)
|
||
IF VL = 128
|
||
TMP_DEST[127:0] := ARITHMETIC_RIGHT_SHIFT_WORDS_128b(SRC1[127:0], SRC2)
|
||
FI;
|
||
IF VL = 256
|
||
TMP_DEST[255:0] := ARITHMETIC_RIGHT_SHIFT_WORDS_256b(SRC1[255:0], SRC2)
|
||
FI;
|
||
IF VL = 512
|
||
TMP_DEST[255:0] := ARITHMETIC_RIGHT_SHIFT_WORDS_256b(SRC1[255:0], SRC2)
|
||
TMP_DEST[511:256] := ARITHMETIC_RIGHT_SHIFT_WORDS_256b(SRC1[511:256], SRC2)
|
||
FI;
|
||
FOR j := 0 TO KL-1
|
||
i := j * 16
|
||
IF k1[j] OR *no writemask*
|
||
THEN DEST[i+15:i] := TMP_DEST[i+15:i]
|
||
ELSE
|
||
IF *merging-masking* ; merging-masking
|
||
THEN *DEST[i+15:i] remains unchanged*
|
||
ELSE *zeroing-masking*
|
||
; zeroing-masking
|
||
DEST[i+15:i] = 0
|
||
FI
|
||
FI;
|
||
ENDFOR
|
||
DEST[MAXVL-1:VL] := 0
|
||
</pre>
|
||
<h3 id="vpsraw--evex-versions--imm8-">VPSRAW (EVEX Versions, imm8)<a class="anchor" href="#vpsraw--evex-versions--imm8-">
|
||
¶
|
||
</a></h3>
|
||
<pre>(KL, VL) = (8, 128), (16, 256), (32, 512)
|
||
IF VL = 128
|
||
TMP_DEST[127:0] := ARITHMETIC_RIGHT_SHIFT_WORDS_128b(SRC1[127:0], imm8)
|
||
FI;
|
||
IF VL = 256
|
||
TMP_DEST[255:0] := ARITHMETIC_RIGHT_SHIFT_WORDS_256b(SRC1[255:0], imm8)
|
||
FI;
|
||
IF VL = 512
|
||
TMP_DEST[255:0] := ARITHMETIC_RIGHT_SHIFT_WORDS_256b(SRC1[255:0], imm8)
|
||
TMP_DEST[511:256] := ARITHMETIC_RIGHT_SHIFT_WORDS_256b(SRC1[511:256], imm8)
|
||
FI;
|
||
FOR j := 0 TO KL-1
|
||
i := j * 16
|
||
IF k1[j] OR *no writemask*
|
||
THEN DEST[i+15:i] := TMP_DEST[i+15:i]
|
||
ELSE
|
||
IF *merging-masking*
|
||
; merging-masking
|
||
THEN *DEST[i+15:i] remains unchanged*
|
||
ELSE *zeroing-masking*
|
||
; zeroing-masking
|
||
DEST[i+15:i] = 0
|
||
FI
|
||
FI;
|
||
ENDFOR
|
||
DEST[MAXVL-1:VL] := 0
|
||
</pre>
|
||
<h3 id="vpsraw--ymm--ymm--xmm-m128----vex">VPSRAW (ymm, ymm, xmm/m128) - VEX<a class="anchor" href="#vpsraw--ymm--ymm--xmm-m128----vex">
|
||
¶
|
||
</a></h3>
|
||
<pre>DEST[255:0] := ARITHMETIC_RIGHT_SHIFT_WORDS_256b(SRC1, SRC2)
|
||
DEST[MAXVL-1:256] := 0
|
||
</pre>
|
||
<h3 id="vpsraw--ymm--imm8----vex">VPSRAW (ymm, imm8) - VEX<a class="anchor" href="#vpsraw--ymm--imm8----vex">
|
||
¶
|
||
</a></h3>
|
||
<pre>DEST[255:0] := ARITHMETIC_RIGHT_SHIFT_WORDS_256b(SRC1, imm8)
|
||
DEST[MAXVL-1:256] := 0
|
||
</pre>
|
||
<h3 id="vpsraw--xmm--xmm--xmm-m128----vex">VPSRAW (xmm, xmm, xmm/m128) - VEX<a class="anchor" href="#vpsraw--xmm--xmm--xmm-m128----vex">
|
||
¶
|
||
</a></h3>
|
||
<pre>DEST[127:0] := ARITHMETIC_RIGHT_SHIFT_WORDS(SRC1, SRC2)
|
||
DEST[MAXVL-1:128] := 0
|
||
</pre>
|
||
<h3 id="vpsraw--xmm--imm8----vex">VPSRAW (xmm, imm8) - VEX<a class="anchor" href="#vpsraw--xmm--imm8----vex">
|
||
¶
|
||
</a></h3>
|
||
<pre>DEST[127:0] := ARITHMETIC_RIGHT_SHIFT_WORDS(SRC1, imm8)
|
||
DEST[MAXVL-1:128] := 0
|
||
</pre>
|
||
<h3 id="psraw--xmm--xmm--xmm-m128-">PSRAW (xmm, xmm, xmm/m128)<a class="anchor" href="#psraw--xmm--xmm--xmm-m128-">
|
||
¶
|
||
</a></h3>
|
||
<pre>DEST[127:0] := ARITHMETIC_RIGHT_SHIFT_WORDS(DEST, SRC)
|
||
DEST[MAXVL-1:128] (Unmodified)
|
||
</pre>
|
||
<h3 id="psraw--xmm--imm8-">PSRAW (xmm, imm8)<a class="anchor" href="#psraw--xmm--imm8-">
|
||
¶
|
||
</a></h3>
|
||
<pre>DEST[127:0] := ARITHMETIC_RIGHT_SHIFT_WORDS(DEST, imm8)
|
||
DEST[MAXVL-1:128] (Unmodified)
|
||
</pre>
|
||
<h3 id="vpsrad--evex-versions--imm8-">VPSRAD (EVEX Versions, imm8)<a class="anchor" href="#vpsrad--evex-versions--imm8-">
|
||
¶
|
||
</a></h3>
|
||
<pre>(KL, VL) = (4, 128), (8, 256), (16, 512)
|
||
FOR j := 0 TO KL-1
|
||
i := j * 32
|
||
IF k1[j] OR *no writemask* THEN
|
||
IF (EVEX.b = 1) AND (SRC1 *is memory*)
|
||
THEN DEST[i+31:i] := ARITHMETIC_RIGHT_SHIFT_DWORDS1(SRC1[31:0], imm8)
|
||
ELSE DEST[i+31:i] := ARITHMETIC_RIGHT_SHIFT_DWORDS1(SRC1[i+31:i], imm8)
|
||
FI;
|
||
ELSE
|
||
IF *merging-masking* ; merging-masking
|
||
THEN *DEST[i+31:i] remains unchanged*
|
||
ELSE *zeroing-masking*
|
||
; zeroing-masking
|
||
DEST[i+31:i] := 0
|
||
FI
|
||
FI;
|
||
ENDFOR
|
||
DEST[MAXVL-1:VL] := 0
|
||
</pre>
|
||
<h3 id="vpsrad--evex-versions--xmm-m128-">VPSRAD (EVEX Versions, xmm/m128)<a class="anchor" href="#vpsrad--evex-versions--xmm-m128-">
|
||
¶
|
||
</a></h3>
|
||
<pre>(KL, VL) = (4, 128), (8, 256), (16, 512)
|
||
IF VL = 128
|
||
TMP_DEST[127:0] := ARITHMETIC_RIGHT_SHIFT_DWORDS_128b(SRC1[127:0], SRC2)
|
||
FI;
|
||
IF VL = 256
|
||
TMP_DEST[255:0] := ARITHMETIC_RIGHT_SHIFT_DWORDS_256b(SRC1[255:0], SRC2)
|
||
FI;
|
||
IF VL = 512
|
||
TMP_DEST[255:0] := ARITHMETIC_RIGHT_SHIFT_DWORDS_256b(SRC1[255:0], SRC2)
|
||
TMP_DEST[511:256] := ARITHMETIC_RIGHT_SHIFT_DWORDS_256b(SRC1[511:256], SRC2)
|
||
FI;
|
||
FOR j := 0 TO KL-1
|
||
i := j * 32
|
||
IF k1[j] OR *no writemask*
|
||
THEN DEST[i+31:i] := TMP_DEST[i+31:i]
|
||
ELSE
|
||
IF *merging-masking*
|
||
; merging-masking
|
||
THEN *DEST[i+31:i] remains unchanged*
|
||
ELSE *zeroing-masking*
|
||
; zeroing-masking
|
||
DEST[i+31:i] := 0
|
||
FI
|
||
FI;
|
||
ENDFOR
|
||
DEST[MAXVL-1:VL] := 0
|
||
</pre>
|
||
<h3 id="vpsrad--ymm--ymm--xmm-m128----vex">VPSRAD (ymm, ymm, xmm/m128) - VEX<a class="anchor" href="#vpsrad--ymm--ymm--xmm-m128----vex">
|
||
¶
|
||
</a></h3>
|
||
<pre>DEST[255:0] := ARITHMETIC_RIGHT_SHIFT_DWORDS_256b(SRC1, SRC2)
|
||
DEST[MAXVL-1:256] := 0
|
||
</pre>
|
||
<h3 id="vpsrad--ymm--imm8----vex">VPSRAD (ymm, imm8) - VEX<a class="anchor" href="#vpsrad--ymm--imm8----vex">
|
||
¶
|
||
</a></h3>
|
||
<pre>DEST[255:0] := ARITHMETIC_RIGHT_SHIFT_DWORDS_256b(SRC1, imm8)
|
||
DEST[MAXVL-1:256] := 0
|
||
</pre>
|
||
<h3 id="vpsrad--xmm--xmm--xmm-m128----vex">VPSRAD (xmm, xmm, xmm/m128) - VEX<a class="anchor" href="#vpsrad--xmm--xmm--xmm-m128----vex">
|
||
¶
|
||
</a></h3>
|
||
<pre>DEST[127:0] := ARITHMETIC_RIGHT_SHIFT_DWORDS(SRC1, SRC2)
|
||
DEST[MAXVL-1:128] := 0
|
||
</pre>
|
||
<h3 id="vpsrad--xmm--imm8----vex">VPSRAD (xmm, imm8) - VEX<a class="anchor" href="#vpsrad--xmm--imm8----vex">
|
||
¶
|
||
</a></h3>
|
||
<pre>DEST[127:0] := ARITHMETIC_RIGHT_SHIFT_DWORDS(SRC1, imm8)
|
||
DEST[MAXVL-1:128] := 0
|
||
</pre>
|
||
<h3 id="psrad--xmm--xmm--xmm-m128-">PSRAD (xmm, xmm, xmm/m128)<a class="anchor" href="#psrad--xmm--xmm--xmm-m128-">
|
||
¶
|
||
</a></h3>
|
||
<pre>DEST[127:0] := ARITHMETIC_RIGHT_SHIFT_DWORDS(DEST, SRC)
|
||
DEST[MAXVL-1:128] (Unmodified)
|
||
</pre>
|
||
<h3 id="psrad--xmm--imm8-">PSRAD (xmm, imm8)<a class="anchor" href="#psrad--xmm--imm8-">
|
||
¶
|
||
</a></h3>
|
||
<pre>DEST[127:0] := ARITHMETIC_RIGHT_SHIFT_DWORDS(DEST, imm8)
|
||
DEST[MAXVL-1:128] (Unmodified)
|
||
</pre>
|
||
<h3 id="vpsraq--evex-versions--imm8-">VPSRAQ (EVEX Versions, imm8)<a class="anchor" href="#vpsraq--evex-versions--imm8-">
|
||
¶
|
||
</a></h3>
|
||
<pre>(KL, VL) = (2, 128), (4, 256), (8, 512)
|
||
FOR j := 0 TO KL-1
|
||
i := j * 64
|
||
IF k1[j] OR *no writemask* THEN
|
||
IF (EVEX.b = 1) AND (SRC1 *is memory*)
|
||
THEN DEST[i+63:i] := ARITHMETIC_RIGHT_SHIFT_QWORDS1(SRC1[63:0], imm8)
|
||
ELSE DEST[i+63:i] := ARITHMETIC_RIGHT_SHIFT_QWORDS1(SRC1[i+63:i], imm8)
|
||
FI;
|
||
ELSE
|
||
IF *merging-masking* ; merging-masking
|
||
THEN *DEST[i+63:i] remains unchanged*
|
||
ELSE *zeroing-masking*
|
||
; zeroing-masking
|
||
DEST[i+63:i] := 0
|
||
FI
|
||
FI;
|
||
ENDFOR
|
||
DEST[MAXVL-1:VL] := 0
|
||
</pre>
|
||
<h3 id="vpsraq--evex-versions--xmm-m128-">VPSRAQ (EVEX Versions, xmm/m128)<a class="anchor" href="#vpsraq--evex-versions--xmm-m128-">
|
||
¶
|
||
</a></h3>
|
||
<pre>(KL, VL) = (2, 128), (4, 256), (8, 512)
|
||
TMP_DEST[VL-1:0] := ARITHMETIC_RIGHT_SHIFT_QWORDS(SRC1[VL-1:0], SRC2, VL)
|
||
FOR j := 0 TO 7
|
||
i := j * 64
|
||
IF k1[j] OR *no writemask*
|
||
THEN DEST[i+63:i] := TMP_DEST[i+63:i]
|
||
ELSE
|
||
IF *merging-masking*
|
||
THEN *DEST[i+63:i] remains unchanged*
|
||
ELSE *zeroing-masking*
|
||
; zeroing-masking
|
||
DEST[i+63:i] := 0
|
||
FI
|
||
FI;
|
||
ENDFOR
|
||
DEST[MAXVL-1:VL] := 0
|
||
</pre>
|
||
<h2 id="intel-c-c++-compiler-intrinsic-equivalents">Intel C/C++ Compiler Intrinsic Equivalents<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalents">
|
||
¶
|
||
</a></h2>
|
||
<pre>VPSRAD __m512i _mm512_srai_epi32(__m512i a, unsigned int imm);
|
||
</pre>
|
||
<pre>VPSRAD __m512i _mm512_mask_srai_epi32(__m512i s, __mmask16 k, __m512i a, unsigned int imm);
|
||
</pre>
|
||
<pre>VPSRAD __m512i _mm512_maskz_srai_epi32( __mmask16 k, __m512i a, unsigned int imm);
|
||
</pre>
|
||
<pre>VPSRAD __m256i _mm256_mask_srai_epi32(__m256i s, __mmask8 k, __m256i a, unsigned int imm);
|
||
</pre>
|
||
<pre>VPSRAD __m256i _mm256_maskz_srai_epi32( __mmask8 k, __m256i a, unsigned int imm);
|
||
</pre>
|
||
<pre>VPSRAD __m128i _mm_mask_srai_epi32(__m128i s, __mmask8 k, __m128i a, unsigned int imm);
|
||
</pre>
|
||
<pre>VPSRAD __m128i _mm_maskz_srai_epi32( __mmask8 k, __m128i a, unsigned int imm);
|
||
</pre>
|
||
<pre>VPSRAD __m512i _mm512_sra_epi32(__m512i a, __m128i cnt);
|
||
</pre>
|
||
<pre>VPSRAD __m512i _mm512_mask_sra_epi32(__m512i s, __mmask16 k, __m512i a, __m128i cnt);
|
||
</pre>
|
||
<pre>VPSRAD __m512i _mm512_maskz_sra_epi32( __mmask16 k, __m512i a, __m128i cnt);
|
||
</pre>
|
||
<pre>VPSRAD __m256i _mm256_mask_sra_epi32(__m256i s, __mmask8 k, __m256i a, __m128i cnt);
|
||
</pre>
|
||
<pre>VPSRAD __m256i _mm256_maskz_sra_epi32( __mmask8 k, __m256i a, __m128i cnt);
|
||
</pre>
|
||
<pre>VPSRAD __m128i _mm_mask_sra_epi32(__m128i s, __mmask8 k, __m128i a, __m128i cnt);
|
||
</pre>
|
||
<pre>VPSRAD __m128i _mm_maskz_sra_epi32( __mmask8 k, __m128i a, __m128i cnt);
|
||
</pre>
|
||
<pre>VPSRAQ __m512i _mm512_srai_epi64(__m512i a, unsigned int imm);
|
||
</pre>
|
||
<pre>VPSRAQ __m512i _mm512_mask_srai_epi64(__m512i s, __mmask8 k, __m512i a, unsigned int imm)
|
||
</pre>
|
||
<pre>VPSRAQ __m512i _mm512_maskz_srai_epi64( __mmask8 k, __m512i a, unsigned int imm)
|
||
</pre>
|
||
<pre>VPSRAQ __m256i _mm256_mask_srai_epi64(__m256i s, __mmask8 k, __m256i a, unsigned int imm);
|
||
</pre>
|
||
<pre>VPSRAQ __m256i _mm256_maskz_srai_epi64( __mmask8 k, __m256i a, unsigned int imm);
|
||
</pre>
|
||
<pre>VPSRAQ __m128i _mm_mask_srai_epi64(__m128i s, __mmask8 k, __m128i a, unsigned int imm);
|
||
</pre>
|
||
<pre>VPSRAQ __m128i _mm_maskz_srai_epi64( __mmask8 k, __m128i a, unsigned int imm);
|
||
</pre>
|
||
<pre>VPSRAQ __m512i _mm512_sra_epi64(__m512i a, __m128i cnt);
|
||
</pre>
|
||
<pre>VPSRAQ __m512i _mm512_mask_sra_epi64(__m512i s, __mmask8 k, __m512i a, __m128i cnt)
|
||
</pre>
|
||
<pre>VPSRAQ __m512i _mm512_maskz_sra_epi64( __mmask8 k, __m512i a, __m128i cnt)
|
||
</pre>
|
||
<pre>VPSRAQ __m256i _mm256_mask_sra_epi64(__m256i s, __mmask8 k, __m256i a, __m128i cnt);
|
||
</pre>
|
||
<pre>VPSRAQ __m256i _mm256_maskz_sra_epi64( __mmask8 k, __m256i a, __m128i cnt);
|
||
</pre>
|
||
<pre>VPSRAQ __m128i _mm_mask_sra_epi64(__m128i s, __mmask8 k, __m128i a, __m128i cnt);
|
||
</pre>
|
||
<pre>VPSRAQ __m128i _mm_maskz_sra_epi64( __mmask8 k, __m128i a, __m128i cnt);
|
||
</pre>
|
||
<pre>VPSRAW __m512i _mm512_srai_epi16(__m512i a, unsigned int imm);
|
||
</pre>
|
||
<pre>VPSRAW __m512i _mm512_mask_srai_epi16(__m512i s, __mmask32 k, __m512i a, unsigned int imm);
|
||
</pre>
|
||
<pre>VPSRAW __m512i _mm512_maskz_srai_epi16( __mmask32 k, __m512i a, unsigned int imm);
|
||
</pre>
|
||
<pre>VPSRAW __m256i _mm256_mask_srai_epi16(__m256i s, __mmask16 k, __m256i a, unsigned int imm);
|
||
</pre>
|
||
<pre>VPSRAW __m256i _mm256_maskz_srai_epi16( __mmask16 k, __m256i a, unsigned int imm);
|
||
</pre>
|
||
<pre>VPSRAW __m128i _mm_mask_srai_epi16(__m128i s, __mmask8 k, __m128i a, unsigned int imm);
|
||
</pre>
|
||
<pre>VPSRAW __m128i _mm_maskz_srai_epi16( __mmask8 k, __m128i a, unsigned int imm);
|
||
</pre>
|
||
<pre>VPSRAW __m512i _mm512_sra_epi16(__m512i a, __m128i cnt);
|
||
</pre>
|
||
<pre>VPSRAW __m512i _mm512_mask_sra_epi16(__m512i s, __mmask16 k, __m512i a, __m128i cnt);
|
||
</pre>
|
||
<pre>VPSRAW __m512i _mm512_maskz_sra_epi16( __mmask16 k, __m512i a, __m128i cnt);
|
||
</pre>
|
||
<pre>VPSRAW __m256i _mm256_mask_sra_epi16(__m256i s, __mmask8 k, __m256i a, __m128i cnt);
|
||
</pre>
|
||
<pre>VPSRAW __m256i _mm256_maskz_sra_epi16( __mmask8 k, __m256i a, __m128i cnt);
|
||
</pre>
|
||
<pre>VPSRAW __m128i _mm_mask_sra_epi16(__m128i s, __mmask8 k, __m128i a, __m128i cnt);
|
||
</pre>
|
||
<pre>VPSRAW __m128i _mm_maskz_sra_epi16( __mmask8 k, __m128i a, __m128i cnt);
|
||
</pre>
|
||
<pre>PSRAW __m64 _mm_srai_pi16 (__m64 m, int count)
|
||
</pre>
|
||
<pre>PSRAW __m64 _mm_sra_pi16 (__m64 m, __m64 count)
|
||
</pre>
|
||
<pre>(V)PSRAW __m128i _mm_srai_epi16(__m128i m, int count)
|
||
</pre>
|
||
<pre>(V)PSRAW __m128i _mm_sra_epi16(__m128i m, __m128i count)
|
||
</pre>
|
||
<pre>VPSRAW __m256i _mm256_srai_epi16 (__m256i m, int count)
|
||
</pre>
|
||
<pre>VPSRAW __m256i _mm256_sra_epi16 (__m256i m, __m128i count)
|
||
</pre>
|
||
<pre>PSRAD __m64 _mm_srai_pi32 (__m64 m, int count)
|
||
</pre>
|
||
<pre>PSRAD __m64 _mm_sra_pi32 (__m64 m, __m64 count)
|
||
</pre>
|
||
<pre>(V)PSRAD __m128i _mm_srai_epi32 (__m128i m, int count)
|
||
</pre>
|
||
<pre>(V)PSRAD __m128i _mm_sra_epi32 (__m128i m, __m128i count)
|
||
</pre>
|
||
<pre>VPSRAD __m256i _mm256_srai_epi32 (__m256i m, int count)
|
||
</pre>
|
||
<pre>VPSRAD __m256i _mm256_sra_epi32 (__m256i m, __m128i count)
|
||
</pre>
|
||
<h2 id="flags-affected">Flags Affected<a class="anchor" href="#flags-affected">
|
||
¶
|
||
</a></h2>
|
||
<p>None.</p>
|
||
<h2 class="exceptions" id="numeric-exceptions">Numeric Exceptions<a class="anchor" href="#numeric-exceptions">
|
||
¶
|
||
</a></h2>
|
||
<p>None.</p>
|
||
<h2 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
|
||
¶
|
||
</a></h2>
|
||
<ul>
|
||
<li>VEX-encoded instructions:
|
||
<ul>
|
||
<li>Syntax with RM/RVM operand encoding (A/C in the operand encoding table), see<span class="not-imported">Table 2-21</span>, “Type 4 Class Exception Conditions.”</li>
|
||
<li>Syntax with RM/RVM operand encoding (A/C in the operand encoding table), see<span class="not-imported">Table 2-21</span>, “Type 4 Class Exception Conditions.”</li>
|
||
<li>Syntax with MI/VMI operand encoding (B/D in the operand encoding table), see<span class="not-imported">Table 2-24</span>, “Type 7 Class Exception Conditions.”</li>
|
||
<li>Syntax with MI/VMI operand encoding (B/D in the operand encoding table), see<span class="not-imported">Table 2-24</span>, “Type 7 Class Exception Conditions.”</li></ul></li>
|
||
<li>EVEX-encoded VPSRAW (E in the operand encoding table), see Exceptions Type E4NF.nb in <span class="not-imported">Table 2-50</span>, “Type E4NF Class Exception Conditions.”</li>
|
||
<li>EVEX-encoded VPSRAD/Q:
|
||
<ul>
|
||
<li>Syntax with Mem128 tuple type (G in the operand encoding table), see Exceptions Type E4NF.nb in <span class="not-imported">Table 2-50</span>, “Type E4NF Class Exception Conditions.”</li>
|
||
<li>Syntax with Mem128 tuple type (G in the operand encoding table), see Exceptions Type E4NF.nb in <span class="not-imported">Table 2-50</span>, “Type E4NF Class Exception Conditions.”</li>
|
||
<li>Syntax with Full tuple type (F in the operand encoding table), see<span class="not-imported">Table 2-49</span>, “Type E4 Class Exception Conditions.”</li>
|
||
<li>Syntax with Full tuple type (F in the operand encoding table), see<span class="not-imported">Table 2-49</span>, “Type E4 Class Exception Conditions.”</li></ul></li></ul><footer><p>
|
||
This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
|
||
inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
|
||
ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
|
||
</p></footer></body></html>
|