forked from NRZCode/ia32-64
96 lines
5.6 KiB
HTML
96 lines
5.6 KiB
HTML
<!DOCTYPE html>
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>PREFETCHh
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— Prefetch Data Into Caches</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>PREFETCHh
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— Prefetch Data Into Caches</h1>
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<table>
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<tr>
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<th>Opcode</th>
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<th>Instruction</th>
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<th>Op/En</th>
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<th>64-Bit Mode</th>
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<th>Compat/Leg Mode</th>
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<th>Description</th></tr>
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<tr>
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<td>0F 18 /1</td>
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<td>PREFETCHT0 m8</td>
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<td>M</td>
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<td>Valid</td>
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<td>Valid</td>
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<td>Move data from m8 closer to the processor using T0 hint.</td></tr>
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<tr>
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<td>0F 18 /2</td>
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<td>PREFETCHT1 m8</td>
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<td>M</td>
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<td>Valid</td>
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<td>Valid</td>
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<td>Move data from m8 closer to the processor using T1 hint.</td></tr>
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<tr>
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<td>0F 18 /3</td>
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<td>PREFETCHT2 m8</td>
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<td>M</td>
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<td>Valid</td>
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<td>Valid</td>
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<td>Move data from m8 closer to the processor using T2 hint.</td></tr>
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<tr>
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<td>0F 18 /0</td>
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<td>PREFETCHNTA m8</td>
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<td>M</td>
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<td>Valid</td>
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<td>Valid</td>
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<td>Move data from m8 closer to the processor using NTA hint.</td></tr></table>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Operand 3</th>
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<th>Operand 4</th></tr>
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<tr>
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<td>M</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td>
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<td>N/A</td>
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<td>N/A</td></tr></table>
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<h2 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h2>
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<p>Fetches the line of data from memory that contains the byte specified with the source operand to a location in the cache hierarchy specified by a locality hint:</p>
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<ul>
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<li>T0 (temporal data)—prefetch data into all levels of the cache hierarchy.</li>
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<li>T1 (temporal data with respect to first level cache misses)—prefetch data into level 2 cache and higher.</li>
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<li>T2 (temporal data with respect to second level cache misses)—prefetch data into level 3 cache and higher, or an implementation-specific choice.</li>
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<li>NTA (non-temporal data with respect to all cache levels)—prefetch data into non-temporal cache structure and into a location close to the processor, minimizing cache pollution.</li></ul>
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<p>The source operand is a byte memory location. (The locality hints are encoded into the machine level instruction using bits 3 through 5 of the ModR/M byte.)</p>
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<p>If the line selected is already present in the cache hierarchy at a level closer to the processor, no data movement occurs. Prefetches from uncacheable or WC memory are ignored.</p>
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<p>The PREFETCH<em>h</em> instruction is merely a hint and does not affect program behavior. If executed, this instruction moves data closer to the processor in anticipation of future use.</p>
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<p>The implementation of prefetch locality hints is implementation-dependent, and can be overloaded or ignored by a processor implementation. The amount of data prefetched is also processor implementation-dependent. It will, however, be a minimum of 32 bytes. Additional details of the implementation-dependent locality hints are described in Section 7.4 of Intel® 64 and IA-32 Architectures Optimization Reference Manual.</p>
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<p>It should be noted that processors are free to speculatively fetch and cache data from system memory regions that are assigned a memory-type that permits speculative reads (that is, the WB, WC, and WT memory types). A PREFETCH<em>h</em> instruction is considered a hint to this speculative behavior. Because this speculative fetching can occur at any time and is not tied to instruction execution, a PREFETCH<em>h</em> instruction is not ordered with respect to the fence instructions (MFENCE, SFENCE, and LFENCE) or locked memory references. A PREFETCH<em>h</em> instruction is also unordered with respect to CLFLUSH and CLFLUSHOPT instructions, other PREFETCH<em>h</em> instructions, or any other general instruction. It is ordered with respect to serializing instructions such as CPUID, WRMSR, OUT, and MOV CR.</p>
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<p>This instruction’s operation is the same in non-64-bit modes and 64-bit mode.</p>
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<h2 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h2>
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<pre>FETCH (m8);
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</pre>
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<h2 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
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¶
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</a></h2>
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<pre>void _mm_prefetch(char *p, int i)
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</pre>
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<pre>The argument “*p” gives the address of the byte (and corresponding cache line) to be prefetched. The value “i” gives a constant (_MM_HINT_T0, _MM_HINT_T1, _MM_HINT_T2, or _MM_HINT_NTA) that specifies the type of prefetch operation to be performed.
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</pre>
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<h2 class="exceptions" id="numeric-exceptions">Numeric Exceptions<a class="anchor" href="#numeric-exceptions">
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¶
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</a></h2>
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<p>None.</p>
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<h2 id="exceptions--all-operating-modes-">Exceptions (All Operating Modes)<a class="anchor" href="#exceptions--all-operating-modes-">
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¶
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</a></h2>
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<p>#UD If the LOCK prefix is used.</p><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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