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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>PMULLD/PMULLQ
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— Multiply Packed Integers and Store Low Result</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>PMULLD/PMULLQ
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— Multiply Packed Integers and Store Low Result</h1>
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<table>
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<tr>
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<th>Opcode/Instruction</th>
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<th>Op/En</th>
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<th>64/32 bit Mode Support</th>
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<th>CPUID Feature Flag</th>
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<th>Description</th></tr>
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<tr>
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<td>66 0F 38 40 /r PMULLD xmm1, xmm2/m128</td>
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<td>A</td>
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<td>V/V</td>
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<td>SSE4_1</td>
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<td>Multiply the packed dword signed integers in xmm1 and xmm2/m128 and store the low 32 bits of each product in xmm1.</td></tr>
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<tr>
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<td>VEX.128.66.0F38.WIG 40 /r VPMULLD xmm1, xmm2, xmm3/m128</td>
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<td>B</td>
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<td>V/V</td>
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<td>AVX</td>
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<td>Multiply the packed dword signed integers in xmm2 and xmm3/m128 and store the low 32 bits of each product in xmm1.</td></tr>
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<tr>
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<td>VEX.256.66.0F38.WIG 40 /r VPMULLD ymm1, ymm2, ymm3/m256</td>
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<td>B</td>
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<td>V/V</td>
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<td>AVX2</td>
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<td>Multiply the packed dword signed integers in ymm2 and ymm3/m256 and store the low 32 bits of each product in ymm1.</td></tr>
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<tr>
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<td>EVEX.128.66.0F38.W0 40 /r VPMULLD xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcst</td>
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<td>C</td>
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<td>V/V</td>
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<td>AVX512VL AVX512F</td>
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<td>Multiply the packed dword signed integers in xmm2 and xmm3/m128/m32bcst and store the low 32 bits of each product in xmm1 under writemask k1.</td></tr>
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<tr>
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<td>EVEX.256.66.0F38.W0 40 /r VPMULLD ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcst</td>
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<td>C</td>
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<td>V/V</td>
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<td>AVX512VL AVX512F</td>
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<td>Multiply the packed dword signed integers in ymm2 and ymm3/m256/m32bcst and store the low 32 bits of each product in ymm1 under writemask k1.</td></tr>
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<tr>
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<td>EVEX.512.66.0F38.W0 40 /r VPMULLD zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst</td>
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<td>C</td>
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<td>V/V</td>
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<td>AVX512F</td>
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<td>Multiply the packed dword signed integers in zmm2 and zmm3/m512/m32bcst and store the low 32 bits of each product in zmm1 under writemask k1.</td></tr>
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<tr>
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<td>EVEX.128.66.0F38.W1 40 /r VPMULLQ xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcst</td>
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<td>C</td>
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<td>V/V</td>
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<td>AVX512VL AVX512DQ</td>
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<td>Multiply the packed qword signed integers in xmm2 and xmm3/m128/m64bcst and store the low 64 bits of each product in xmm1 under writemask k1.</td></tr>
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<tr>
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<td>EVEX.256.66.0F38.W1 40 /r VPMULLQ ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcst</td>
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<td>C</td>
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<td>V/V</td>
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<td>AVX512VLA VX512DQ</td>
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<td>Multiply the packed qword signed integers in ymm2 and ymm3/m256/m64bcst and store the low 64 bits of each product in ymm1 under writemask k1.</td></tr>
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<tr>
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<td>EVEX.512.66.0F38.W1 40 /r VPMULLQ zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst</td>
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<td>C</td>
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<td>V/V</td>
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<td>AVX512DQ</td>
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<td>Multiply the packed qword signed integers in zmm2 and zmm3/m512/m64bcst and store the low 64 bits of each product in zmm1 under writemask k1.</td></tr></table>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Tuple Type</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Operand 3</th>
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<th>Operand 4</th></tr>
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<tr>
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<td>A</td>
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<td>N/A</td>
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<td>ModRM:reg (r, w)</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td>
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<td>N/A</td></tr>
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<tr>
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<td>B</td>
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<td>N/A</td>
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<td>ModRM:reg (w)</td>
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<td>VEX.vvvv (r)</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td></tr>
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<tr>
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<td>C</td>
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<td>Full</td>
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<td>ModRM:reg (w)</td>
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<td>EVEX.vvvv (r)</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td></tr></table>
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<h2 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h2>
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<p>Performs a SIMD signed multiply of the packed signed dword/qword integers from each element of the first source operand with the corresponding element in the second source operand. The low 32/64 bits of each 64/128-bit intermediate results are stored to the destination operand.</p>
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<p>128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source operand is an XMM register or a 128-bit memory location. Bits (MAXVL-1:128) of the corresponding ZMM destination register remain unchanged.</p>
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<p>VEX.128 encoded version: The first source and destination operands are XMM registers. The second source operand is an XMM register or a 128-bit memory location. Bits (MAXVL-1:128) of the corresponding ZMM register are zeroed.</p>
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<p>VEX.256 encoded version: The first source operand is a YMM register; The second source operand is a YMM register or 256-bit memory location. Bits (MAXVL-1:256) of the corresponding destination ZMM register are zeroed.</p>
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<p>EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 32/64-bit memory location. The destination operand is conditionally updated based on writemask k1.</p>
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<h2 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h2>
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<h3 id="vpmullq--evex-encoded-versions-">VPMULLQ (EVEX Encoded Versions)<a class="anchor" href="#vpmullq--evex-encoded-versions-">
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¶
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</a></h3>
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<pre>(KL, VL) = (2, 128), (4, 256), (8, 512)
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FOR j := 0 TO KL-1
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i := j * 64
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IF k1[j] OR *no writemask* THEN
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IF (EVEX.b == 1) AND (SRC2 *is memory*)
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THEN Temp[127:0] := SRC1[i+63:i] * SRC2[63:0]
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ELSE Temp[127:0] := SRC1[i+63:i] * SRC2[i+63:i]
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FI;
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DEST[i+63:i] := Temp[63:0]
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ELSE
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IF *merging-masking* ; merging-masking
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THEN *DEST[i+63:i] remains unchanged*
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ELSE ; zeroing-masking
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DEST[i+63:i] := 0
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FI
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FI;
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ENDFOR
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DEST[MAXVL-1:VL] := 0
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</pre>
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<h3 id="vpmulld--evex-encoded-versions-">VPMULLD (EVEX Encoded Versions)<a class="anchor" href="#vpmulld--evex-encoded-versions-">
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¶
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</a></h3>
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<pre>(KL, VL) = (4, 128), (8, 256), (16, 512)
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FOR j := 0 TO KL-1
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i := j * 32
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IF k1[j] OR *no writemask* THEN
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IF (EVEX.b = 1) AND (SRC2 *is memory*)
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THEN Temp[63:0] := SRC1[i+31:i] * SRC2[31:0]
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ELSE Temp[63:0] := SRC1[i+31:i] * SRC2[i+31:i]
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FI;
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DEST[i+31:i] := Temp[31:0]
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ELSE
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IF *merging-masking* ; merging-masking
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*DEST[i+31:i] remains unchanged*
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ELSE
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; zeroing-masking
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DEST[i+31:i] := 0
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FI
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FI;
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ENDFOR
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DEST[MAXVL-1:VL] := 0
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</pre>
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<h3 id="vpmulld--vex-256-encoded-version-">VPMULLD (VEX.256 Encoded Version)<a class="anchor" href="#vpmulld--vex-256-encoded-version-">
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¶
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</a></h3>
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<pre>Temp0[63:0] := SRC1[31:0] * SRC2[31:0]
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Temp1[63:0] := SRC1[63:32] * SRC2[63:32]
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Temp2[63:0] := SRC1[95:64] * SRC2[95:64]
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Temp3[63:0] := SRC1[127:96] * SRC2[127:96]
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Temp4[63:0] := SRC1[159:128] * SRC2[159:128]
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Temp5[63:0] := SRC1[191:160] * SRC2[191:160]
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Temp6[63:0] := SRC1[223:192] * SRC2[223:192]
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Temp7[63:0] := SRC1[255:224] * SRC2[255:224]
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DEST[31:0] := Temp0[31:0]
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DEST[63:32] := Temp1[31:0]
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DEST[95:64] := Temp2[31:0]
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DEST[127:96] := Temp3[31:0]
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DEST[159:128] := Temp4[31:0]
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DEST[191:160] := Temp5[31:0]
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DEST[223:192] := Temp6[31:0]
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DEST[255:224] := Temp7[31:0]
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DEST[MAXVL-1:256] := 0
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</pre>
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<h3 id="vpmulld--vex-128-encoded-version-">VPMULLD (VEX.128 Encoded Version)<a class="anchor" href="#vpmulld--vex-128-encoded-version-">
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¶
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</a></h3>
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<pre>Temp0[63:0] := SRC1[31:0] * SRC2[31:0]
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Temp1[63:0] := SRC1[63:32] * SRC2[63:32]
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Temp2[63:0] := SRC1[95:64] * SRC2[95:64]
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Temp3[63:0] := SRC1[127:96] * SRC2[127:96]
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DEST[31:0] := Temp0[31:0]
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DEST[63:32] := Temp1[31:0]
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DEST[95:64] := Temp2[31:0]
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DEST[127:96] := Temp3[31:0]
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DEST[MAXVL-1:128] := 0
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</pre>
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<h3 id="pmulld--128-bit-legacy-sse-version-">PMULLD (128-bit Legacy SSE Version)<a class="anchor" href="#pmulld--128-bit-legacy-sse-version-">
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¶
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</a></h3>
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<pre>Temp0[63:0] := DEST[31:0] * SRC[31:0]
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Temp1[63:0] := DEST[63:32] * SRC[63:32]
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Temp2[63:0] := DEST[95:64] * SRC[95:64]
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Temp3[63:0] := DEST[127:96] * SRC[127:96]
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DEST[31:0] := Temp0[31:0]
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DEST[63:32] := Temp1[31:0]
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DEST[95:64] := Temp2[31:0]
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DEST[127:96] := Temp3[31:0]
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DEST[MAXVL-1:128] (Unmodified)
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</pre>
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<h2 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
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¶
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</a></h2>
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<pre>VPMULLD __m512i _mm512_mullo_epi32(__m512i a, __m512i b);
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</pre>
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<pre>VPMULLD __m512i _mm512_mask_mullo_epi32(__m512i s, __mmask16 k, __m512i a, __m512i b);
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</pre>
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<pre>VPMULLD __m512i _mm512_maskz_mullo_epi32( __mmask16 k, __m512i a, __m512i b);
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</pre>
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<pre>VPMULLD __m256i _mm256_mask_mullo_epi32(__m256i s, __mmask8 k, __m256i a, __m256i b);
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</pre>
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<pre>VPMULLD __m256i _mm256_maskz_mullo_epi32( __mmask8 k, __m256i a, __m256i b);
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</pre>
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<pre>VPMULLD __m128i _mm_mask_mullo_epi32(__m128i s, __mmask8 k, __m128i a, __m128i b);
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</pre>
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<pre>VPMULLD __m128i _mm_maskz_mullo_epi32( __mmask8 k, __m128i a, __m128i b);
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</pre>
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<pre>VPMULLD __m256i _mm256_mullo_epi32(__m256i a, __m256i b);
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</pre>
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<pre>PMULLD __m128i _mm_mullo_epi32(__m128i a, __m128i b);
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</pre>
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<pre>VPMULLQ __m512i _mm512_mullo_epi64(__m512i a, __m512i b);
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</pre>
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<pre>VPMULLQ __m512i _mm512_mask_mullo_epi64(__m512i s, __mmask8 k, __m512i a, __m512i b);
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</pre>
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<pre>VPMULLQ __m512i _mm512_maskz_mullo_epi64( __mmask8 k, __m512i a, __m512i b);
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</pre>
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<pre>VPMULLQ __m256i _mm256_mullo_epi64(__m256i a, __m256i b);
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</pre>
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<pre>VPMULLQ __m256i _mm256_mask_mullo_epi64(__m256i s, __mmask8 k, __m256i a, __m256i b);
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</pre>
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<pre>VPMULLQ __m256i _mm256_maskz_mullo_epi64( __mmask8 k, __m256i a, __m256i b);
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</pre>
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<pre>VPMULLQ __m128i _mm_mullo_epi64(__m128i a, __m128i b);
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</pre>
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<pre>VPMULLQ __m128i _mm_mask_mullo_epi64(__m128i s, __mmask8 k, __m128i a, __m128i b);
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</pre>
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<pre>VPMULLQ __m128i _mm_maskz_mullo_epi64( __mmask8 k, __m128i a, __m128i b);
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</pre>
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<h2 class="exceptions" id="simd-floating-point-exceptions">SIMD Floating-Point Exceptions<a class="anchor" href="#simd-floating-point-exceptions">
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¶
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</a></h2>
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<p>None.</p>
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<h2 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
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¶
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</a></h2>
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<p>Non-EVEX-encoded instruction, see <span class="not-imported">Table 2-21</span>, “Type 4 Class Exception Conditions.”</p>
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<p>EVEX-encoded instruction, see <span class="not-imported">Table 2-49</span>, “Type E4 Class Exception Conditions.”</p><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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