forked from NRZCode/ia32-64
370 lines
43 KiB
HTML
370 lines
43 KiB
HTML
<!DOCTYPE html>
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>PHADDW/PHADDD
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— Packed Horizontal Add</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>PHADDW/PHADDD
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— Packed Horizontal Add</h1>
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<table>
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<tr>
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<th>Opcode/Instruction</th>
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<th>Op/En</th>
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<th>64/32 bit Mode Support</th>
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<th>CPUID Feature Flag</th>
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<th>Description</th></tr>
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<tr>
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<td>NP 0F 38 01 /r<sup>1</sup> PHADDW mm1, mm2/m64</td>
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<td>RM</td>
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<td>V/V</td>
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<td>SSSE3</td>
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<td>Add 16-bit integers horizontally, pack to mm1.</td></tr>
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<tr>
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<td>66 0F 38 01 /r PHADDW xmm1, xmm2/m128</td>
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<td>RM</td>
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<td>V/V</td>
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<td>SSSE3</td>
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<td>Add 16-bit integers horizontally, pack to xmm1.</td></tr>
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<tr>
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<td>NP 0F 38 02 /r PHADDD mm1, mm2/m64</td>
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<td>RM</td>
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<td>V/V</td>
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<td>SSSE3</td>
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<td>Add 32-bit integers horizontally, pack to mm1.</td></tr>
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<tr>
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<td>66 0F 38 02 /r PHADDD xmm1, xmm2/m128</td>
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<td>RM</td>
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<td>V/V</td>
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<td>SSSE3</td>
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<td>Add 32-bit integers horizontally, pack to xmm1.</td></tr>
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<tr>
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<td>VEX.128.66.0F38.WIG 01 /r VPHADDW xmm1, xmm2, xmm3/m128</td>
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<td>RVM</td>
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<td>V/V</td>
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<td>AVX</td>
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<td>Add 16-bit integers horizontally, pack to xmm1.</td></tr>
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<tr>
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<td>VEX.128.66.0F38.WIG 02 /r VPHADDD xmm1, xmm2, xmm3/m128</td>
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<td>RVM</td>
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<td>V/V</td>
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<td>AVX</td>
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<td>Add 32-bit integers horizontally, pack to xmm1.</td></tr>
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<tr>
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<td>VEX.256.66.0F38.WIG 01 /r VPHADDW ymm1, ymm2, ymm3/m256</td>
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<td>RVM</td>
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<td>V/V</td>
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<td>AVX2</td>
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<td>Add 16-bit signed integers horizontally, pack to ymm1.</td></tr>
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<tr>
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<td>VEX.256.66.0F38.WIG 02 /r VPHADDD ymm1, ymm2, ymm3/m256</td>
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<td>RVM</td>
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<td>V/V</td>
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<td>AVX2</td>
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<td>Add 32-bit signed integers horizontally, pack to ymm1.</td></tr></table>
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<blockquote>
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<p>1. See note in Section 2.5, “Intel® AVX and Intel® SSE Instruction Exception Classification,” in the Intel<sup>®</sup> 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A, and Section 23.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers,” in the Intel<sup>®</sup> 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.</p></blockquote>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Operand 3</th>
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<th>Operand 4</th></tr>
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<tr>
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<td>RM</td>
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<td>ModRM:reg (r, w)</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td>
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<td>N/A</td></tr>
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<tr>
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<td>RVM</td>
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<td>ModRM:reg (w)</td>
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<td>VEX.vvvv (r)</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td></tr></table>
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<h2 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h2>
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<p>(V)PHADDW adds two adjacent 16-bit signed integers horizontally from the source and destination operands and packs the 16-bit signed results to the destination operand (first operand). (V)PHADDD adds two adjacent 32-bit signed integers horizontally from the source and destination operands and packs the 32-bit signed results to the destination operand (first operand). When the source operand is a 128-bit memory operand, the operand must be aligned on a 16-byte boundary or a general-protection exception (#GP) will be generated.</p>
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<p>Note that these instructions can operate on either unsigned or signed (two’s complement notation) integers; however, it does not set bits in the EFLAGS register to indicate overflow and/or a carry. To prevent undetected overflow conditions, software must control the ranges of the values operated on.</p>
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<p>Legacy SSE instructions: Both operands can be MMX registers. The second source operand can be an MMX register or a 64-bit memory location.</p>
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<p>128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source operand can be an XMM register or a 128-bit memory location. Bits (MAXVL-1:128) of the corresponding YMM destination register remain unchanged.</p>
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<p>In 64-bit mode, use the REX prefix to access additional registers.</p>
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<p>VEX.128 encoded version: The first source and destination operands are XMM registers. The second source operand can be an XMM register or a 128-bit memory location. Bits (MAXVL-1:128) of the corresponding YMM register are zeroed.</p>
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<p>VEX.256 encoded version: Horizontal addition of two adjacent data elements of the low 16-bytes of the first and second source operands are packed into the low 16-bytes of the destination operand. Horizontal addition of two adjacent data elements of the high 16-bytes of the first and second source operands are packed into the high 16-bytes of the destination operand. The first source and destination operands are YMM registers. The second source operand can be an YMM register or a 256-bit memory location.</p>
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||
<p>S7 S3 S3 S4 S3 S2 S1 S0</p>
|
||
<figure id="fig-4-10">
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<path d="M 388.8 4.800000000000068 L 388.92 4.620000000000118 L 388.5 4.380000000000109 L 388.38 4.560000000000059" style="fill: rgb(0%, 0%, 0%); fill-rule: nonzero"></path>
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<path d="M 299.22 36.12000000000006 L 299.1 36.30000000000007 L 298.68 36.00000000000006 L 298.8 35.82000000000005" style="fill: rgb(0%, 0%, 0%); fill-rule: nonzero"></path>
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<path d="M 321.18 4.680000000000064 L 320.76 4.380000000000109 L 298.8 35.82000000000005 L 299.22 36.12000000000006" style="fill: rgb(0%, 0%, 0%); fill-rule: nonzero"></path>
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<path d="M 268.98 38.58000000000004 L 268.74 38.940000000000055 L 269.64000000000004 39.54000000000002 L 269.88 39.180000000000064" style="fill: rgb(0%, 0%, 0%); fill-rule: nonzero"></path>
|
||
<path d="M 269.28000000000003 39.240000000000066 L 269.64000000000004 37.62000000000006 L 269.76000000000005 36.60000000000008 L 270.54 37.440000000000055 L 274.26000000000005 41.58000000000004 L 275.34000000000003 42.84000000000009 L 273.72 42.36000000000007 L 268.38000000000005 40.86000000000007 L 267.42 40.62000000000006 L 268.14000000000004 40.02000000000004 L 268.68 39.90000000000009 L 274.02000000000004 41.40000000000009 L 273.72 42.36000000000007 L 273.48 42.240000000000066 L 269.76000000000005 38.10000000000008 L 270.54 37.440000000000055 L 270.6 37.86000000000007 L 270.24 39.480000000000075" style="fill: rgb(0%, 0%, 0%); fill-rule: nonzero"></path>
|
||
<path d="M 268.14 40.02000000000004 L 269.4 39.00000000000006 L 270.24 39.48000000000002 L 270.24 39.660000000000025 L 270.06 39.78000000000003 L 268.8 40.80000000000001" style="fill: rgb(0%, 0%, 0%); fill-rule: nonzero"></path>
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<path d="M 269.76 39.36000000000007 L 270.12 37.740000000000066 L 273.84 41.88000000000005 L 268.5 40.38000000000005" style="fill: rgb(0%, 0%, 0%); fill-rule: evenodd"></path>
|
||
<path d="M 211.86 2.7000000000000455 L 211.68 2.580000000000041 L 211.44000000000003 3.0 L 211.62 3.1200000000000045" style="fill: rgb(0%, 0%, 0%); fill-rule: nonzero"></path>
|
||
<path d="M 268.98 38.58000000000004 L 269.16 38.700000000000045 L 268.92 39.12000000000006 L 268.74 39.00000000000006" style="fill: rgb(0%, 0%, 0%); fill-rule: nonzero"></path>
|
||
<path d="M 211.86 2.7000000000000455 L 211.62 3.1200000000000045 L 268.74 39.00000000000006 L 268.98 38.58000000000004" style="fill: rgb(0%, 0%, 0%); fill-rule: nonzero"></path>
|
||
<text lengthAdjust="spacingAndGlyphs" style="font-size: 8.917955999999947pt; fill: #000" textLength="13.320996999999977" x="241.14079099999998" y="41.46577440000004">255</text>
|
||
<text lengthAdjust="spacingAndGlyphs" style="font-size: 8.917956pt; fill: #000" textLength="4.442995999999994" x="394.56" y="41.88610100000005">0</text>
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 8.917956000000004pt; fill: #000" textLength="16.45586629999997" x="229.32" y="58.32610100000005">Dest</text></g></svg>
|
||
<figcaption><a href='phaddw.phaddd.html#fig-4-10'>Figure 4-10</a>. 256-bit VPHADDD Instruction Operation</figcaption></figure>
|
||
<h2 id="operation">Operation<a class="anchor" href="#operation">
|
||
¶
|
||
</a></h2>
|
||
<h3 id="phaddw--with-64-bit-operands-">PHADDW (With 64-bit Operands)<a class="anchor" href="#phaddw--with-64-bit-operands-">
|
||
¶
|
||
</a></h3>
|
||
<pre>mm1[15-0] = mm1[31-16] + mm1[15-0];
|
||
mm1[31-16] = mm1[63-48] + mm1[47-32];
|
||
mm1[47-32] = mm2/m64[31-16] + mm2/m64[15-0];
|
||
mm1[63-48] = mm2/m64[63-48] + mm2/m64[47-32];
|
||
</pre>
|
||
<h3 id="phaddw--with-128-bit-operands-">PHADDW (With 128-bit Operands)<a class="anchor" href="#phaddw--with-128-bit-operands-">
|
||
¶
|
||
</a></h3>
|
||
<pre>xmm1[15-0] = xmm1[31-16] + xmm1[15-0];
|
||
xmm1[31-16] = xmm1[63-48] + xmm1[47-32];
|
||
xmm1[47-32] = xmm1[95-80] + xmm1[79-64];
|
||
xmm1[63-48] = xmm1[127-112] + xmm1[111-96];
|
||
xmm1[79-64] = xmm2/m128[31-16] + xmm2/m128[15-0];
|
||
xmm1[95-80] = xmm2/m128[63-48] + xmm2/m128[47-32];
|
||
xmm1[111-96] = xmm2/m128[95-80] + xmm2/m128[79-64];
|
||
xmm1[127-112] = xmm2/m128[127-112] + xmm2/m128[111-96];
|
||
</pre>
|
||
<h3 id="vphaddw--vex-128-encoded-version-">VPHADDW (VEX.128 Encoded Version)<a class="anchor" href="#vphaddw--vex-128-encoded-version-">
|
||
¶
|
||
</a></h3>
|
||
<pre>DEST[15:0] := SRC1[31:16] + SRC1[15:0]
|
||
DEST[31:16] := SRC1[63:48] + SRC1[47:32]
|
||
DEST[47:32] := SRC1[95:80] + SRC1[79:64]
|
||
DEST[63:48] := SRC1[127:112] + SRC1[111:96]
|
||
DEST[79:64] := SRC2[31:16] + SRC2[15:0]
|
||
DEST[95:80] := SRC2[63:48] + SRC2[47:32]
|
||
DEST[111:96] := SRC2[95:80] + SRC2[79:64]
|
||
DEST[127:112] := SRC2[127:112] + SRC2[111:96]
|
||
DEST[MAXVL-1:128] := 0
|
||
</pre>
|
||
<h3 id="vphaddw--vex-256-encoded-version-">VPHADDW (VEX.256 Encoded Version)<a class="anchor" href="#vphaddw--vex-256-encoded-version-">
|
||
¶
|
||
</a></h3>
|
||
<pre>DEST[15:0] := SRC1[31:16] + SRC1[15:0]
|
||
DEST[31:16] := SRC1[63:48] + SRC1[47:32]
|
||
DEST[47:32] := SRC1[95:80] + SRC1[79:64]
|
||
DEST[63:48] := SRC1[127:112] + SRC1[111:96]
|
||
DEST[79:64] := SRC2[31:16] + SRC2[15:0]
|
||
DEST[95:80] := SRC2[63:48] + SRC2[47:32]
|
||
DEST[111:96] := SRC2[95:80] + SRC2[79:64]
|
||
DEST[127:112] := SRC2[127:112] + SRC2[111:96]
|
||
DEST[143:128] := SRC1[159:144] + SRC1[143:128]
|
||
DEST[159:144] := SRC1[191:176] + SRC1[175:160]
|
||
DEST[175:160] := SRC1[223:208] + SRC1[207:192]
|
||
DEST[191:176] := SRC1[255:240] + SRC1[239:224]
|
||
DEST[207:192] := SRC2[127:112] + SRC2[143:128]
|
||
DEST[223:208] := SRC2[159:144] + SRC2[175:160]
|
||
DEST[239:224] := SRC2[191:176] + SRC2[207:192]
|
||
DEST[255:240] := SRC2[223:208] + SRC2[239:224]
|
||
</pre>
|
||
<h3 id="phaddd--with-64-bit-operands-">PHADDD (With 64-bit Operands)<a class="anchor" href="#phaddd--with-64-bit-operands-">
|
||
¶
|
||
</a></h3>
|
||
<pre>mm1[31-0] = mm1[63-32] + mm1[31-0];
|
||
mm1[63-32] = mm2/m64[63-32] + mm2/m64[31-0];
|
||
</pre>
|
||
<h3 id="phaddd--with-128-bit-operands-">PHADDD (With 128-bit Operands)<a class="anchor" href="#phaddd--with-128-bit-operands-">
|
||
¶
|
||
</a></h3>
|
||
<pre>xmm1[31-0] = xmm1[63-32] + xmm1[31-0];
|
||
xmm1[63-32] = xmm1[127-96] + xmm1[95-64];
|
||
xmm1[95-64] = xmm2/m128[63-32] + xmm2/m128[31-0];
|
||
xmm1[127-96] = xmm2/m128[127-96] + xmm2/m128[95-64];
|
||
</pre>
|
||
<h3 id="vphaddd--vex-128-encoded-version-">VPHADDD (VEX.128 Encoded Version)<a class="anchor" href="#vphaddd--vex-128-encoded-version-">
|
||
¶
|
||
</a></h3>
|
||
<pre>DEST[31-0] := SRC1[63-32] + SRC1[31-0]
|
||
DEST[63-32] := SRC1[127-96] + SRC1[95-64]
|
||
DEST[95-64] := SRC2[63-32] + SRC2[31-0]
|
||
DEST[127-96] := SRC2[127-96] + SRC2[95-64]
|
||
DEST[MAXVL-1:128] := 0
|
||
</pre>
|
||
<h3 id="vphaddd--vex-256-encoded-version-">VPHADDD (VEX.256 Encoded Version)<a class="anchor" href="#vphaddd--vex-256-encoded-version-">
|
||
¶
|
||
</a></h3>
|
||
<pre>DEST[31-0] := SRC1[63-32] + SRC1[31-0]
|
||
DEST[63-32] := SRC1[127-96] + SRC1[95-64]
|
||
DEST[95-64] := SRC2[63-32] + SRC2[31-0]
|
||
DEST[127-96] := SRC2[127-96] + SRC2[95-64]
|
||
DEST[159-128] := SRC1[191-160] + SRC1[159-128]
|
||
DEST[191-160] := SRC1[255-224] + SRC1[223-192]
|
||
DEST[223-192] := SRC2[191-160] + SRC2[159-128]
|
||
DEST[255-224] := SRC2[255-224] + SRC2[223-192]
|
||
</pre>
|
||
<h2 id="intel-c-c++-compiler-intrinsic-equivalents">Intel C/C++ Compiler Intrinsic Equivalents<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalents">
|
||
¶
|
||
</a></h2>
|
||
<pre>PHADDW __m64 _mm_hadd_pi16 (__m64 a, __m64 b)
|
||
</pre>
|
||
<pre>PHADDD __m64 _mm_hadd_pi32 (__m64 a, __m64 b)
|
||
</pre>
|
||
<pre>(V)PHADDW __m128i _mm_hadd_epi16 (__m128i a, __m128i b)
|
||
</pre>
|
||
<pre>(V)PHADDD __m128i _mm_hadd_epi32 (__m128i a, __m128i b)
|
||
</pre>
|
||
<pre>VPHADDW __m256i _mm256_hadd_epi16 (__m256i a, __m256i b)
|
||
</pre>
|
||
<pre>VPHADDD __m256i _mm256_hadd_epi32 (__m256i a, __m256i b)
|
||
</pre>
|
||
<h2 class="exceptions" id="simd-floating-point-exceptions">SIMD Floating-Point Exceptions<a class="anchor" href="#simd-floating-point-exceptions">
|
||
¶
|
||
</a></h2>
|
||
<p>None.</p>
|
||
<h2 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
|
||
¶
|
||
</a></h2>
|
||
<p>See <span class="not-imported">Table 2-21</span>, “Type 4 Class Exception Conditions,” additionally:</p>
|
||
<table>
|
||
<tr>
|
||
<td>#UD</td>
|
||
<td>If VEX.L = 1.</td></tr></table><footer><p>
|
||
This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
|
||
inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
|
||
ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
|
||
</p></footer></body></html>
|