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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>PCMPEQQ
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— Compare Packed Qword Data for Equal</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>PCMPEQQ
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— Compare Packed Qword Data for Equal</h1>
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<table>
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<tr>
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<th>Opcode/Instruction</th>
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<th>Op/En</th>
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<th>64/32 bit Mode Support</th>
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<th>CPUID Feature Flag</th>
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<th>Description</th></tr>
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<tr>
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<td>66 0F 38 29 /r PCMPEQQ xmm1, xmm2/m128</td>
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<td>A</td>
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<td>V/V</td>
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<td>SSE4_1</td>
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<td>Compare packed qwords in xmm2/m128 and xmm1 for equality.</td></tr>
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<tr>
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<td>VEX.128.66.0F38.WIG 29 /r VPCMPEQQ xmm1, xmm2, xmm3/m128</td>
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<td>B</td>
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<td>V/V</td>
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<td>AVX</td>
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<td>Compare packed quadwords in xmm3/m128 and xmm2 for equality.</td></tr>
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<tr>
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<td>VEX.256.66.0F38.WIG 29 /r VPCMPEQQ ymm1, ymm2, ymm3 /m256</td>
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<td>B</td>
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<td>V/V</td>
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<td>AVX2</td>
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<td>Compare packed quadwords in ymm3/m256 and ymm2 for equality.</td></tr>
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<tr>
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<td>EVEX.128.66.0F38.W1 29 /r VPCMPEQQ k1 {k2}, xmm2, xmm3/m128/m64bcst</td>
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<td>C</td>
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<td>V/V</td>
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<td>AVX512VL AVX512F</td>
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<td>Compare Equal between int64 vector xmm2 and int64 vector xmm3/m128/m64bcst, and set vector mask k1 to reflect the zero/nonzero status of each element of the result, under writemask.</td></tr>
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<tr>
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<td>EVEX.256.66.0F38.W1 29 /r VPCMPEQQ k1 {k2}, ymm2, ymm3/m256/m64bcst</td>
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<td>C</td>
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<td>V/V</td>
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<td>AVX512VL AVX512F</td>
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<td>Compare Equal between int64 vector ymm2 and int64 vector ymm3/m256/m64bcst, and set vector mask k1 to reflect the zero/nonzero status of each element of the result, under writemask.</td></tr>
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<tr>
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<td>EVEX.512.66.0F38.W1 29 /r VPCMPEQQ k1 {k2}, zmm2, zmm3/m512/m64bcst</td>
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<td>C</td>
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<td>V/V</td>
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<td>AVX512F</td>
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<td>Compare Equal between int64 vector zmm2 and int64 vector zmm3/m512/m64bcst, and set vector mask k1 to reflect the zero/nonzero status of each element of the result, under writemask.</td></tr></table>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Tuple Type</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Operand 3</th>
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<th>Operand 4</th></tr>
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<tr>
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<td>A</td>
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<td>N/A</td>
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<td>ModRM:reg (r, w)</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td>
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<td>N/A</td></tr>
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<tr>
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<td>B</td>
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<td>N/A</td>
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<td>ModRM:reg (w)</td>
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<td>VEX.vvvv (r)</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td></tr>
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<tr>
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<td>C</td>
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<td>Full</td>
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<td>ModRM:reg (w)</td>
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<td>EVEX.vvvv (r)</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td></tr></table>
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<h2 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h2>
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<p>Performs an SIMD compare for equality of the packed quadwords in the destination operand (first operand) and the source operand (second operand). If a pair of data elements is equal, the corresponding data element in the destination is set to all 1s; otherwise, it is set to 0s.</p>
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<p>128-bit Legacy SSE version: The second source operand can be an XMM register or a 128-bit memory location. The first source and destination operands are XMM registers. Bits (MAXVL-1:128) of the corresponding YMM destination register remain unchanged.</p>
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<p>VEX.128 encoded version: The second source operand can be an XMM register or a 128-bit memory location. The first source and destination operands are XMM registers. Bits (MAXVL-1:128) of the corresponding YMM register are zeroed.</p>
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<p>VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register or a 256-bit memory location. The destination operand is a YMM register.</p>
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<p>EVEX encoded VPCMPEQQ: The first source operand (second operand) is a ZMM/YMM/XMM register. The second source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 64-bit memory location. The destination operand (first operand) is a mask register updated according to the writemask k2.</p>
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<h2 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h2>
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<h3 id="pcmpeqq--with-128-bit-operands-">PCMPEQQ (With 128-bit Operands)<a class="anchor" href="#pcmpeqq--with-128-bit-operands-">
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¶
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</a></h3>
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<pre>IF (DEST[63:0] = SRC[63:0])
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THEN DEST[63:0] := FFFFFFFFFFFFFFFFH;
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ELSE DEST[63:0] := 0; FI;
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IF (DEST[127:64] = SRC[127:64])
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THEN DEST[127:64] := FFFFFFFFFFFFFFFFH;
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ELSE DEST[127:64] := 0; FI;
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DEST[MAXVL-1:128] (Unmodified)
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</pre>
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<h3 id="compare_qwords_equal--src1--src2-">COMPARE_QWORDS_EQUAL (SRC1, SRC2)<a class="anchor" href="#compare_qwords_equal--src1--src2-">
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¶
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</a></h3>
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<pre>IF SRC1[63:0] = SRC2[63:0]
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THEN DEST[63:0] := FFFFFFFFFFFFFFFFH;
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ELSE DEST[63:0] := 0; FI;
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IF SRC1[127:64] = SRC2[127:64]
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THEN DEST[127:64] := FFFFFFFFFFFFFFFFH;
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ELSE DEST[127:64] := 0; FI;
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</pre>
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<h3 id="vpcmpeqq--vex-128-encoded-version-">VPCMPEQQ (VEX.128 Encoded Version)<a class="anchor" href="#vpcmpeqq--vex-128-encoded-version-">
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¶
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</a></h3>
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<pre>DEST[127:0] := COMPARE_QWORDS_EQUAL(SRC1,SRC2)
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DEST[MAXVL-1:128] := 0
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</pre>
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<h3 id="vpcmpeqq--vex-256-encoded-version-">VPCMPEQQ (VEX.256 Encoded Version)<a class="anchor" href="#vpcmpeqq--vex-256-encoded-version-">
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¶
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</a></h3>
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<pre>DEST[127:0] := COMPARE_QWORDS_EQUAL(SRC1[127:0],SRC2[127:0])
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DEST[255:128] := COMPARE_QWORDS_EQUAL(SRC1[255:128],SRC2[255:128])
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DEST[MAXVL-1:256] := 0
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</pre>
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<h3 id="vpcmpeqq--evex-encoded-versions-">VPCMPEQQ (EVEX Encoded Versions)<a class="anchor" href="#vpcmpeqq--evex-encoded-versions-">
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¶
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</a></h3>
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<pre>(KL, VL) = (2, 128), (4, 256), (8, 512)
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FOR j := 0 TO KL-1
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i := j * 64
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IF k2[j] OR *no writemask*
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THEN
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IF (EVEX.b = 1) AND (SRC2 *is memory*)
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THEN CMP := SRC1[i+63:i] = SRC2[63:0];
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ELSE CMP := SRC1[i+63:i] = SRC2[i+63:i];
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FI;
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IF CMP = TRUE
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THEN DEST[j] := 1;
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ELSE DEST[j] := 0; FI;
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ELSE DEST[j] := 0
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; zeroing-masking only
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FI;
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ENDFOR
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DEST[MAX_KL-1:KL] := 0
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</pre>
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<h2 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
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¶
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</a></h2>
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<pre>VPCMPEQQ __mmask8 _mm512_cmpeq_epi64_mask( __m512i a, __m512i b);
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</pre>
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<pre>VPCMPEQQ __mmask8 _mm512_mask_cmpeq_epi64_mask(__mmask8 k, __m512i a, __m512i b);
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</pre>
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<pre>VPCMPEQQ __mmask8 _mm256_cmpeq_epi64_mask( __m256i a, __m256i b);
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</pre>
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<pre>VPCMPEQQ __mmask8 _mm256_mask_cmpeq_epi64_mask(__mmask8 k, __m256i a, __m256i b);
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</pre>
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<pre>VPCMPEQQ __mmask8 _mm_cmpeq_epi64_mask( __m128i a, __m128i b);
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</pre>
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<pre>VPCMPEQQ __mmask8 _mm_mask_cmpeq_epi64_mask(__mmask8 k, __m128i a, __m128i b);
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</pre>
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<pre>(V)PCMPEQQ __m128i _mm_cmpeq_epi64(__m128i a, __m128i b);
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</pre>
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<pre>VPCMPEQQ __m256i _mm256_cmpeq_epi64( __m256i a, __m256i b);
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</pre>
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<h2 id="flags-affected">Flags Affected<a class="anchor" href="#flags-affected">
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¶
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</a></h2>
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<p>None.</p>
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<h2 class="exceptions" id="simd-floating-point-exceptions">SIMD Floating-Point Exceptions<a class="anchor" href="#simd-floating-point-exceptions">
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¶
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</a></h2>
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<p>None.</p>
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<h2 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
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¶
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</a></h2>
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<p>Non-EVEX-encoded instruction, see <span class="not-imported">Table 2-21</span>, “Type 4 Class Exception Conditions.”</p>
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<p>EVEX-encoded VPCMPEQQ, see <span class="not-imported">Table 2-49</span>, “Type E4 Class Exception Conditions.”</p><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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