drginfo/ia32-64
1
0
Fork 0
forked from NRZCode/ia32-64
Code Pull requests Activity
ia32-64/x86/parameters.html
NRZ Code 92622c37d6 Initial commit
2025-07-08 02:23:29 -03:00

234 lines
12 KiB
HTML
Raw Permalink Blame History

This file contains ambiguous Unicode characters

This file contains Unicode characters that might be confused with other characters. If you think that this is intentional, you can safely ignore this warning. Use the Escape button to reveal them.

<!DOCTYPE html>
<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>GETSEC[PARAMETERS]
— Report the SMX Parameters</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>GETSEC[PARAMETERS]
— Report the SMX Parameters</h1>
<table>
<tr>
<th>Opcode</th>
<th>Instruction</th>
<th>Description</th></tr>
<tr>
<td>NP 0F 37 (EAX=6)</td>
<td>GETSEC[PARAMETERS]</td>
<td>Report the SMX parameters. The parameters index is input in EBX with the result returned in EAX, EBX, and ECX.</td></tr></table>
<h2 id="description">Description<a class="anchor" href="#description">
</a></h2>
<p>The GETSEC[PARAMETERS] instruction returns specific parameter information for SMX features supported by the processor. Parameter information is returned in EAX, EBX, and ECX, with the input parameter selected using EBX.</p>
<p>Software retrieves parameter information by searching with an input index for EBX starting at 0, and then reading the returned results in EAX, EBX, and ECX. EAX[4:0] is designated to return a parameter type field indicating if a parameter is available and what type it is. If EAX[4:0] is returned with 0, this designates a null parameter and indicates no more parameters are available.</p>
<p><span class="not-imported">Table 7-7</span> defines the parameter types supported in current and future implementations.</p>
<figure id="tbl-7-7">
<table>
<tr>
<th>Parameter Type EAX[4:0]</th>
<th>Parameter Description</th>
<th>EAX[31:5]</th>
<th>EBX[31:0]</th>
<th>ECX[31:0]</th></tr>
<tr>
<td>0</td>
<td>NULL</td>
<td>Reserved (0 returned)</td>
<td>Reserved (unmodified)</td>
<td>Reserved (unmodified)</td></tr>
<tr>
<td>1</td>
<td>Supported AC module versions</td>
<td>Reserved (0 returned)</td>
<td>Version comparison mask</td>
<td>Version numbers supported</td></tr>
<tr>
<td>2</td>
<td>Max size of authenticated code execution area</td>
<td>Multiply by 32 for size in bytes</td>
<td>Reserved (unmodified)</td>
<td>Reserved (unmodified)</td></tr>
<tr>
<td>3</td>
<td>External memory types supported during AC mode</td>
<td>Memory type bit mask</td>
<td>Reserved (unmodified)</td>
<td>Reserved (unmodified)</td></tr>
<tr>
<td>4</td>
<td>Selective SENTER functionality control</td>
<td>EAX[14:8] correspond to available SENTER function disable controls</td>
<td>Reserved (unmodified)</td>
<td>Reserved (unmodified)</td></tr>
<tr>
<td>5</td>
<td>TXT extensions support</td>
<td>TXT Feature Extensions Flags (see Table )</td>
<td>Reserved</td>
<td>Reserved</td></tr>
<tr>
<td>6-31</td>
<td>Undefined</td>
<td>Reserved (unmodified)</td>
<td>Reserved (unmodified)</td>
<td>Reserved (unmodified)</td></tr></table>
<figcaption><span class="not-imported">Table 7-7</span>. SMX Reporting Parameters Format</figcaption></figure>
<figure id="tbl-7-8">
<table>
<tr>
<th>Bit</th>
<th>Definition</th>
<th>Description</th></tr>
<tr>
<td>5</td>
<td>Processor based S-CRTM support</td>
<td>Returns 1 if this processor implements a processor-rooted S-CRTM capability and 0 if not (S-CRTM is rooted in BIOS). This flag cannot be used to infer whether the chipset supports TXT or whether the processor support SMX.</td></tr>
<tr>
<td>6</td>
<td>Machine Check Handling</td>
<td>Returns 1 if it machine check status registers can be preserved through ENTERACCS and SENTER. If this bit is 1, the caller of ENTERACCS and SENTER is not required to clear machine check error status bits before invoking these GETSEC leaves. If this bit returns 0, the caller of ENTERACCS and SENTER must clear all machine check error status bits before invoking these GETSEC leaves.</td></tr>
<tr>
<td>31:7</td>
<td>Reserved</td>
<td>Reserved for future use. Will return 0.</td></tr></table>
<figcaption><span class="not-imported">Table 7-8</span>. TXT Feature Extensions Flags</figcaption></figure>
<p>Supported AC module versions (as defined by the AC module HeaderVersion field) can be determined for a particular SMX capable processor by the type 1 parameter. Using EBX to index through the available parameters reported by GETSEC[PARAMETERS] for each unique parameter set returned for type 1, software can determine the complete list of AC module version(s) supported.</p>
<p>For each parameter set, EBX returns the comparison mask and ECX returns the available HeaderVersion field values supported, after AND'ing the target HeaderVersion with the comparison mask. Software can then determine if a particular AC module version is supported by following the pseudo-code search routine given below:</p>
<p>parameter_search_index= 0 do { EBX= parameter_search_index++ EAX= 6 GETSEC if (EAX[4:0] = 1) { if ((version_query &amp; EBX) = ECX) { version_is_supported= 1 break } }</p>
<p>} while (EAX[4:0] ≠ 0)</p>
<p>If only AC modules with a HeaderVersion of 0 are supported by the processor, then only one parameter set of type 1 will be returned, as follows: EAX = 00000001H,</p>
<p>EBX = FFFFFFFFH and ECX = 00000000H.</p>
<p>The maximum capacity for an authenticated code execution area supported by the processor is reported with the parameter type of 2. The maximum supported size in bytes is determined by multiplying the returned size in EAX[31:5] by 32. Thus, for a maximum supported authenticated RAM size of 32KBytes, EAX returns with 00008002H.</p>
<p>Supportable memory types for memory mapped outside of the authenticated code execution area are reported with the parameter type of 3. While is active, as initiated by the GETSEC functions SENTER and ENTERACCS and terminated by EXITAC, there are restrictions on what memory types are allowed for the rest of system memory. It is the responsibility of the system software to initialize the memory type range register (MTRR) MSRs and/or the page attribute table (PAT) to only map memory types consistent with the reporting of this parameter. The reporting of supportable memory types of external memory is indicated using a bit map returned in EAX[31:8]. These bit positions correspond to the memory type encodings defined for the MTRR MSR and PAT programming. See <span class="not-imported">Table 7-9</span>.</p>
<p>The parameter type of 4 is used for enumerating the availability of selective GETSEC[SENTER] function disable controls. If a 1 is reported in bits 14:8 of the returned parameter EAX, then this indicates a disable control capability exists with SENTER for a particular function. The enumerated field in bits 14:8 corresponds to use of the EDX input parameter bits 6:0 for SENTER. If an enumerated field bit is set to 1, then the corresponding EDX input parameter bit of EDX may be set to 1 to disable that designated function. If the enumerated field bit is 0 or this parameter is not reported, then no disable capability exists with the corresponding EDX input parameter for SENTER, and EDX bit(s) must be cleared to 0 to enable execution of SENTER. If no selective disable capability for SENTER exists as enumerated, then the corresponding bits in the IA32_FEATURE_CONTROL MSR bits 14:8 must also be programmed to 1 if the SENTER global enable bit 15 of the MSR is set. This is required to enable future extensibility of SENTER selective disable capability with respect to potentially separate software initialization of the MSR.</p>
<figure id="tbl-7-9">
<table>
<tr>
<th>EAX Bit Position</th>
<th>Parameter Description</th></tr>
<tr>
<td>8</td>
<td>Uncacheable (UC)</td></tr>
<tr>
<td>9</td>
<td>Write Combining (WC)</td></tr>
<tr>
<td>11:10</td>
<td>Reserved</td></tr>
<tr>
<td>12</td>
<td>Write-through (WT)</td></tr>
<tr>
<td>13</td>
<td>Write-protected (WP)</td></tr>
<tr>
<td>14</td>
<td>Write-back (WB)</td></tr>
<tr>
<td>31:15</td>
<td>Reserved</td></tr></table>
<figcaption><span class="not-imported">Table 7-9</span>. External Memory Types Using Parameter 3</figcaption></figure>
<p>If the GETSEC[PARAMETERS] leaf or specific parameter is not present for a given SMX capable processor, then default parameter values should be assumed. These are defined in <span class="not-imported">Table 7-10</span>.</p>
<figure id="tbl-7-10">
<table>
<tr>
<th>Parameter Type EAX[4:0]</th>
<th>Default Setting</th>
<th>Parameter Description</th></tr>
<tr>
<td>1</td>
<td>0.0 only</td>
<td>Supported AC module versions.</td></tr>
<tr>
<td>2</td>
<td>32 KBytes</td>
<td>Authenticated code execution area size.</td></tr>
<tr>
<td>3</td>
<td>UC only</td>
<td>External memory types supported during AC execution mode.</td></tr>
<tr>
<td>4</td>
<td>None</td>
<td>Available SENTER selective disable controls.</td></tr></table>
<figcaption><span class="not-imported">Table 7-10</span>. Default Parameter Values</figcaption></figure>
<h2 id="operation">Operation<a class="anchor" href="#operation">
</a></h2>
<pre>(* example of a processor supporting only a 0.0 HeaderVersion, 32K ACRAM size, memory types UC and WC *)
IF (CR4.SMXE=0)
THEN #UD;
ELSE IF (in VMX non-root operation)
THEN VM Exit (reason=”GETSEC instruction”);
ELSE IF (GETSEC leaf unsupported)
THEN #UD;
(* example of a processor supporting a 0.0 HeaderVersion *)
IF (EBX=0) THEN
EAX := 00000001h;
EBX := FFFFFFFFh;
ECX := 00000000h;
ELSE IF (EBX=1)
(* example of a processor supporting a 32K ACRAM size *)
THEN EAX := 00008002h;
ESE IF (EBX= 2)
(* example of a processor supporting external memory types of UC and WC *)
THEN EAX := 00000303h;
ESE IF (EBX= other value(s) less than unsupported index value)
(* EAX value varies. Consult <span class="not-imported">Table 7-7</span> and Table *)
ELSE (* unsupported index*)
EAX := 00000000h;
END;
</pre>
<h2 id="flags-affected">Flags Affected<a class="anchor" href="#flags-affected">
</a></h2>
<p>None.</p>
<h2 id="use-of-prefixes">Use of Prefixes<a class="anchor" href="#use-of-prefixes">
</a></h2>
<p>LOCK Causes #UD.</p>
<p>REP* Cause #UD (includes REPNE/REPNZ and REP/REPE/REPZ).</p>
<p>Operand size Causes #UD.</p>
<p>NP 66/F2/F3 prefixes are not allowed.</p>
<p>Segmentoverrides Ignored.</p>
<p>Address size Ignored.</p>
<p>REX Ignored.</p>
<h2 class="exceptions" id="protected-mode-exceptions">Protected Mode Exceptions<a class="anchor" href="#protected-mode-exceptions">
</a></h2>
<table>
<tr>
<td rowspan="2">#UD</td>
<td>If CR4.SMXE = 0.</td></tr>
<tr>
<td>If GETSEC[PARAMETERS] is not reported as supported by GETSEC[CAPABILITIES].</td></tr></table>
<h2 class="exceptions" id="real-address-mode-exceptions">Real-Address Mode Exceptions<a class="anchor" href="#real-address-mode-exceptions">
</a></h2>
<table>
<tr>
<td rowspan="2">#UD</td>
<td>If CR4.SMXE = 0.</td></tr>
<tr>
<td>If GETSEC[PARAMETERS] is not reported as supported by GETSEC[CAPABILITIES].</td></tr></table>
<h2 class="exceptions" id="virtual-8086-mode-exceptions">Virtual-8086 Mode Exceptions<a class="anchor" href="#virtual-8086-mode-exceptions">
</a></h2>
<table>
<tr>
<td rowspan="2">#UD</td>
<td>If CR4.SMXE = 0.</td></tr>
<tr>
<td>If GETSEC[PARAMETERS] is not reported as supported by GETSEC[CAPABILITIES].</td></tr></table>
<h2 class="exceptions" id="compatibility-mode-exceptions">Compatibility Mode Exceptions<a class="anchor" href="#compatibility-mode-exceptions">
</a></h2>
<p>All protected mode exceptions apply.</p>
<h2 class="exceptions" id="64-bit-mode-exceptions">64-Bit Mode Exceptions<a class="anchor" href="#64-bit-mode-exceptions">
</a></h2>
<p>All protected mode exceptions apply.</p>
<h2 id="vm-exit-condition">VM-Exit Condition<a class="anchor" href="#vm-exit-condition">
</a></h2>
<p>Reason (GETSEC) If in VMX non-root operation.</p><footer><p>
This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
</p></footer></body></html>
View git blame Copy permalink