forked from NRZCode/ia32-64
97 lines
4.1 KiB
HTML
97 lines
4.1 KiB
HTML
<!DOCTYPE html>
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>NOP
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— No Operation</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>NOP
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— No Operation</h1>
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<table>
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<tr>
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<th>Opcode</th>
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<th>Instruction</th>
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<th>Op/En</th>
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<th>64-Bit Mode</th>
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<th>Compat/Leg Mode</th>
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<th>Description</th></tr>
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<tr>
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<td>NP 90</td>
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<td>NOP</td>
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<td>ZO</td>
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<td>Valid</td>
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<td>Valid</td>
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<td>One byte no-operation instruction.</td></tr>
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<tr>
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<td>NP 0F 1F /0</td>
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<td>NOP r/m16</td>
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<td>M</td>
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<td>Valid</td>
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<td>Valid</td>
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<td>Multi-byte no-operation instruction.</td></tr>
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<tr>
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<td>NP 0F 1F /0</td>
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<td>NOP r/m32</td>
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<td>M</td>
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<td>Valid</td>
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<td>Valid</td>
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<td>Multi-byte no-operation instruction.</td></tr></table>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Operand 3</th>
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<th>Operand 4</th></tr>
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<tr>
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<td>ZO</td>
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<td>N/A</td>
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<td>N/A</td>
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<td>N/A</td>
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<td>N/A</td></tr>
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<tr>
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<td>M</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td>
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<td>N/A</td>
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<td>N/A</td></tr></table>
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<h2 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h2>
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<p>This instruction performs no operation. It is a one-byte or multi-byte NOP that takes up space in the instruction stream but does not impact machine context, except for the EIP register.</p>
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<p>The multi-byte form of NOP is available on processors with model encoding:</p>
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<ul>
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<li>CPUID.01H.EAX[Bytes 11:8] = 0110B or 1111B</li></ul>
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<p>The multi-byte NOP instruction does not alter the content of a register and will not issue a memory operation. The instruction’s operation is the same in non-64-bit modes and 64-bit mode.</p>
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<h2 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h2>
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<pre>The one-byte NOP instruction is an alias mnemonic for the XCHG (E)AX, (E)AX instruction.
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The multi-byte NOP instruction performs no operation on supported processors and generates undefined opcode
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exception on processors that do not support the multi-byte NOP instruction.
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The memory operand form of the instruction allows software to create a byte sequence of “no operation” as one
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instruction. For situations where multiple-byte NOPs are needed, the recommended operations (32-bit mode and
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64-bit mode) are:
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</pre>
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<figure id="tbl-4-12">
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<table>
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<tr>
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<th>Length</th>
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<th>Assembly</th>
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<th>Byte Sequence</th></tr>
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<tr>
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<td>2 bytes 3 bytes 4 bytes 5 bytes 6 bytes 7 bytes 8 bytes 9 bytes</td>
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<td>66 NOP NOP DWORD ptr [EAX] NOP DWORD ptr [EAX + 00H] NOP DWORD ptr [EAX + EAX*1 + 00H] 66 NOP DWORD ptr [EAX + EAX*1 + 00H] NOP DWORD ptr [EAX + 00000000H] NOP DWORD ptr [EAX + EAX*1 + 00000000H] 66 NOP DWORD ptr [EAX + EAX*1 + 00000000H]</td>
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<td>66 90H 0F 1F 00H 0F 1F 40 00H 0F 1F 44 00 00H 66 0F 1F 44 00 00H 0F 1F 80 00 00 00 00H 0F 1F 84 00 00 00 00 00H 66 0F 1F 84 00 00 00 00 00H</td></tr></table>
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<figcaption><a href='nop.html#tbl-4-12'>Table 4-12</a>. Recommended Multi-Byte Sequence of NOP Instruction</figcaption></figure>
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<h2 id="flags-affected">Flags Affected<a class="anchor" href="#flags-affected">
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¶
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</a></h2>
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<p>None.</p>
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<h2 id="exceptions--all-operating-modes-">Exceptions (All Operating Modes)<a class="anchor" href="#exceptions--all-operating-modes-">
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¶
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</a></h2>
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<p>#UD If the LOCK prefix is used.</p><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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