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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>MULSS
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— Multiply Scalar Single Precision Floating-Point Values</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>MULSS
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— Multiply Scalar Single Precision Floating-Point Values</h1>
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<table>
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<tr>
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<th>Opcode/Instruction</th>
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<th>Op / En</th>
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<th>64/32 bit Mode Support</th>
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<th>CPUID Feature Flag</th>
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<th>Description</th></tr>
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<tr>
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<td>F3 0F 59 /r MULSS xmm1,xmm2/m32</td>
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<td>A</td>
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<td>V/V</td>
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<td>SSE</td>
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<td>Multiply the low single precision floating-point value in xmm2/m32 by the low single precision floating-point value in xmm1.</td></tr>
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<tr>
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<td>VEX.LIG.F3.0F.WIG 59 /r VMULSS xmm1,xmm2, xmm3/m32</td>
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<td>B</td>
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<td>V/V</td>
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<td>AVX</td>
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<td>Multiply the low single precision floating-point value in xmm3/m32 by the low single precision floating-point value in xmm2.</td></tr>
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<tr>
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<td>EVEX.LLIG.F3.0F.W0 59 /r VMULSS xmm1 {k1}{z}, xmm2, xmm3/m32 {er}</td>
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<td>C</td>
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<td>V/V</td>
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<td>AVX512F</td>
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<td>Multiply the low single precision floating-point value in xmm3/m32 by the low single precision floating-point value in xmm2.</td></tr></table>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Tuple Type</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Operand 3</th>
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<th>Operand 4</th></tr>
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<tr>
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<td>A</td>
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<td>N/A</td>
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<td>ModRM:reg (r, w)</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td>
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<td>N/A</td></tr>
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<tr>
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<td>B</td>
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<td>N/A</td>
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<td>ModRM:reg (w)</td>
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<td>VEX.vvvv (r)</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td></tr>
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<tr>
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<td>C</td>
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<td>Tuple1 Scalar</td>
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<td>ModRM:reg (w)</td>
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<td>EVEX.vvvv (r)</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td></tr></table>
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<h2 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h2>
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<p>Multiplies the low single precision floating-point value from the second source operand by the low single precision floating-point value in the first source operand, and stores the single precision floating-point result in the destination operand. The second source operand can be an XMM register or a 32-bit memory location. The first source operand and the destination operands are XMM registers.</p>
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<p>128-bit Legacy SSE version: The first source operand and the destination operand are the same. Bits (MAXVL-1:32) of the corresponding YMM destination register remain unchanged.</p>
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<p>VEX.128 and EVEX encoded version: The first source operand is an xmm register encoded by VEX.vvvv. The three high-order doublewords of the destination operand are copied from the first source operand. Bits (MAXVL-1:128) of the destination register are zeroed.</p>
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<p>EVEX encoded version: The low doubleword element of the destination operand is updated according to the write-mask.</p>
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<p>Software should ensure VMULSS is encoded with VEX.L=0. Encoding VMULSS with VEX.L=1 may encounter unpredictable behavior across different processor generations.</p>
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<h2 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h2>
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<h3 id="vmulss--evex-encoded-version-">VMULSS (EVEX Encoded Version)<a class="anchor" href="#vmulss--evex-encoded-version-">
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¶
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</a></h3>
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<pre>IF (EVEX.b = 1) AND SRC2 *is a register*
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THEN
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SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(EVEX.RC);
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ELSE
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SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(MXCSR.RC);
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FI;
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IF k1[0] or *no writemask*
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THEN DEST[31:0] := SRC1[31:0] * SRC2[31:0]
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ELSE
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IF *merging-masking* ; merging-masking
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THEN *DEST[31:0] remains unchanged*
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ELSE ; zeroing-masking
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THEN DEST[31:0] := 0
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FI
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FI;
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ENDFOR
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DEST[127:32] := SRC1[127:32]
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DEST[MAXVL-1:128] := 0
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</pre>
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<h3 id="vmulss--vex-128-encoded-version-">VMULSS (VEX.128 Encoded Version)<a class="anchor" href="#vmulss--vex-128-encoded-version-">
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¶
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</a></h3>
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<pre>DEST[31:0] := SRC1[31:0] * SRC2[31:0]
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DEST[127:32] := SRC1[127:32]
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DEST[MAXVL-1:128] := 0
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</pre>
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<h3 id="mulss--128-bit-legacy-sse-version-">MULSS (128-bit Legacy SSE Version)<a class="anchor" href="#mulss--128-bit-legacy-sse-version-">
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¶
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</a></h3>
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<pre>DEST[31:0] := DEST[31:0] * SRC[31:0]
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DEST[MAXVL-1:32] (Unmodified)
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</pre>
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<h2 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
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¶
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</a></h2>
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<pre>VMULSS __m128 _mm_mask_mul_ss(__m128 s, __mmask8 k, __m128 a, __m128 b);
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</pre>
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<pre>VMULSS __m128 _mm_maskz_mul_ss( __mmask8 k, __m128 a, __m128 b);
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</pre>
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<pre>VMULSS __m128 _mm_mul_round_ss( __m128 a, __m128 b, int);
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</pre>
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<pre>VMULSS __m128 _mm_mask_mul_round_ss(__m128 s, __mmask8 k, __m128 a, __m128 b, int);
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</pre>
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<pre>VMULSS __m128 _mm_maskz_mul_round_ss( __mmask8 k, __m128 a, __m128 b, int);
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</pre>
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<pre>MULSS __m128 _mm_mul_ss(__m128 a, __m128 b)
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</pre>
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<h2 class="exceptions" id="simd-floating-point-exceptions">SIMD Floating-Point Exceptions<a class="anchor" href="#simd-floating-point-exceptions">
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¶
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</a></h2>
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<p>Underflow, Overflow, Invalid, Precision, Denormal.</p>
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<h2 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
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¶
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</a></h2>
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<p>Non-EVEX-encoded instruction, see <span class="not-imported">Table 2-20</span>, “Type 3 Class Exception Conditions.”</p>
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<p>EVEX-encoded instruction, see <span class="not-imported">Table 2-47</span>, “Type E3 Class Exception Conditions.”</p><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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