forked from NRZCode/ia32-64
177 lines
7.9 KiB
HTML
177 lines
7.9 KiB
HTML
<!DOCTYPE html>
|
||
<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>MULPD
|
||
— Multiply Packed Double Precision Floating-Point Values</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>MULPD
|
||
— Multiply Packed Double Precision Floating-Point Values</h1>
|
||
|
||
<table>
|
||
<tr>
|
||
<th>Opcode/Instruction</th>
|
||
<th>Op / En</th>
|
||
<th>64/32 bit Mode Support</th>
|
||
<th>CPUID Feature Flag</th>
|
||
<th>Description</th></tr>
|
||
<tr>
|
||
<td>66 0F 59 /r MULPD xmm1, xmm2/m128</td>
|
||
<td>A</td>
|
||
<td>V/V</td>
|
||
<td>SSE2</td>
|
||
<td>Multiply packed double precision floating-point values in xmm2/m128 with xmm1 and store result in xmm1.</td></tr>
|
||
<tr>
|
||
<td>VEX.128.66.0F.WIG 59 /r VMULPD xmm1,xmm2, xmm3/m128</td>
|
||
<td>B</td>
|
||
<td>V/V</td>
|
||
<td>AVX</td>
|
||
<td>Multiply packed double precision floating-point values in xmm3/m128 with xmm2 and store result in xmm1.</td></tr>
|
||
<tr>
|
||
<td>VEX.256.66.0F.WIG 59 /r VMULPD ymm1, ymm2, ymm3/m256</td>
|
||
<td>B</td>
|
||
<td>V/V</td>
|
||
<td>AVX</td>
|
||
<td>Multiply packed double precision floating-point values in ymm3/m256 with ymm2 and store result in ymm1.</td></tr>
|
||
<tr>
|
||
<td>EVEX.128.66.0F.W1 59 /r VMULPD xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcst</td>
|
||
<td>C</td>
|
||
<td>V/V</td>
|
||
<td>AVX512VL AVX512F</td>
|
||
<td>Multiply packed double precision floating-point values from xmm3/m128/m64bcst to xmm2 and store result in xmm1.</td></tr>
|
||
<tr>
|
||
<td>EVEX.256.66.0F.W1 59 /r VMULPD ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcst</td>
|
||
<td>C</td>
|
||
<td>V/V</td>
|
||
<td>AVX512VL AVX512F</td>
|
||
<td>Multiply packed double precision floating-point values from ymm3/m256/m64bcst to ymm2 and store result in ymm1.</td></tr>
|
||
<tr>
|
||
<td>EVEX.512.66.0F.W1 59 /r VMULPD zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst{er}</td>
|
||
<td>C</td>
|
||
<td>V/V</td>
|
||
<td>AVX512F</td>
|
||
<td>Multiply packed double precision floating-point values in zmm3/m512/m64bcst with zmm2 and store result in zmm1.</td></tr></table>
|
||
<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
|
||
¶
|
||
</a></h2>
|
||
<table>
|
||
<tr>
|
||
<th>Op/En</th>
|
||
<th>Tuple Type</th>
|
||
<th>Operand 1</th>
|
||
<th>Operand 2</th>
|
||
<th>Operand 3</th>
|
||
<th>Operand 4</th></tr>
|
||
<tr>
|
||
<td>A</td>
|
||
<td>N/A</td>
|
||
<td>ModRM:reg (r, w)</td>
|
||
<td>ModRM:r/m (r)</td>
|
||
<td>N/A</td>
|
||
<td>N/A</td></tr>
|
||
<tr>
|
||
<td>B</td>
|
||
<td>N/A</td>
|
||
<td>ModRM:reg (w)</td>
|
||
<td>VEX.vvvv (r)</td>
|
||
<td>ModRM:r/m (r)</td>
|
||
<td>N/A</td></tr>
|
||
<tr>
|
||
<td>C</td>
|
||
<td>Full</td>
|
||
<td>ModRM:reg (w)</td>
|
||
<td>EVEX.vvvv (r)</td>
|
||
<td>ModRM:r/m (r)</td>
|
||
<td>N/A</td></tr></table>
|
||
<h2 id="description">Description<a class="anchor" href="#description">
|
||
¶
|
||
</a></h2>
|
||
<p>Multiply packed double precision floating-point values from the first source operand with corresponding values in the second source operand, and stores the packed double precision floating-point results in the destination operand.</p>
|
||
<p>EVEX encoded versions: The first source operand (the second operand) is a ZMM/YMM/XMM register. The second source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 64-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with writemask k1.</p>
|
||
<p>VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM register or a 256-bit memory location. The destination operand is a YMM register. Bits (MAXVL-1:256) of the corresponding destination ZMM register are zeroed.</p>
|
||
<p>VEX.128 encoded version: The first source operand is a XMM register. The second source operand can be a XMM register or a 128-bit memory location. The destination operand is a XMM register. The upper bits (MAXVL-1:128) of the destination YMM register destination are zeroed.</p>
|
||
<p>128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The destination is not distinct from the first source XMM register and the upper bits (MAXVL-1:128) of the corresponding ZMM register destination are unmodified.</p>
|
||
<h2 id="operation">Operation<a class="anchor" href="#operation">
|
||
¶
|
||
</a></h2>
|
||
<h3 id="vmulpd--evex-encoded-versions-">VMULPD (EVEX Encoded Versions)<a class="anchor" href="#vmulpd--evex-encoded-versions-">
|
||
¶
|
||
</a></h3>
|
||
<pre>(KL, VL) = (2, 128), (4, 256), (8, 512)
|
||
IF (VL = 512) AND (EVEX.b = 1) AND SRC2 *is a register*
|
||
THEN
|
||
SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(EVEX.RC);
|
||
ELSE
|
||
SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(MXCSR.RC);
|
||
FI;
|
||
FOR j := 0 TO KL-1
|
||
i := j * 64
|
||
IF k1[j] OR *no writemask*
|
||
THEN
|
||
IF (EVEX.b = 1) AND (SRC2 *is memory*)
|
||
THEN
|
||
DEST[i+63:i] := SRC1[i+63:i] * SRC2[63:0]
|
||
ELSE
|
||
DEST[i+63:i] := SRC1[i+63:i] * SRC2[i+63:i]
|
||
FI;
|
||
ELSE
|
||
IF *merging-masking* ; merging-masking
|
||
THEN *DEST[i+63:i] remains unchanged*
|
||
ELSE ; zeroing-masking
|
||
DEST[i+63:i] := 0
|
||
FI
|
||
FI;
|
||
ENDFOR
|
||
DEST[MAXVL-1:VL] := 0
|
||
</pre>
|
||
<h3 id="vmulpd--vex-256-encoded-version-">VMULPD (VEX.256 Encoded Version)<a class="anchor" href="#vmulpd--vex-256-encoded-version-">
|
||
¶
|
||
</a></h3>
|
||
<pre>DEST[63:0] := SRC1[63:0] * SRC2[63:0]
|
||
DEST[127:64] := SRC1[127:64] * SRC2[127:64]
|
||
DEST[191:128] := SRC1[191:128] * SRC2[191:128]
|
||
DEST[255:192] := SRC1[255:192] * SRC2[255:192]
|
||
DEST[MAXVL-1:256] := 0;
|
||
.
|
||
</pre>
|
||
<h3 id="vmulpd--vex-128-encoded-version-">VMULPD (VEX.128 Encoded Version)<a class="anchor" href="#vmulpd--vex-128-encoded-version-">
|
||
¶
|
||
</a></h3>
|
||
<pre>DEST[63:0] := SRC1[63:0] * SRC2[63:0]
|
||
DEST[127:64] := SRC1[127:64] * SRC2[127:64]
|
||
DEST[MAXVL-1:128] := 0
|
||
</pre>
|
||
<h3 id="mulpd--128-bit-legacy-sse-version-">MULPD (128-bit Legacy SSE Version)<a class="anchor" href="#mulpd--128-bit-legacy-sse-version-">
|
||
¶
|
||
</a></h3>
|
||
<pre>DEST[63:0] := DEST[63:0] * SRC[63:0]
|
||
DEST[127:64] := DEST[127:64] * SRC[127:64]
|
||
DEST[MAXVL-1:128] (Unmodified)
|
||
</pre>
|
||
<h2 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
|
||
¶
|
||
</a></h2>
|
||
<pre>VMULPD __m512d _mm512_mul_pd( __m512d a, __m512d b);
|
||
</pre>
|
||
<pre>VMULPD __m512d _mm512_mask_mul_pd(__m512d s, __mmask8 k, __m512d a, __m512d b);
|
||
</pre>
|
||
<pre>VMULPD __m512d _mm512_maskz_mul_pd( __mmask8 k, __m512d a, __m512d b);
|
||
</pre>
|
||
<pre>VMULPD __m512d _mm512_mul_round_pd( __m512d a, __m512d b, int);
|
||
</pre>
|
||
<pre>VMULPD __m512d _mm512_mask_mul_round_pd(__m512d s, __mmask8 k, __m512d a, __m512d b, int);
|
||
</pre>
|
||
<pre>VMULPD __m512d _mm512_maskz_mul_round_pd( __mmask8 k, __m512d a, __m512d b, int);
|
||
</pre>
|
||
<pre>VMULPD __m256d _mm256_mul_pd (__m256d a, __m256d b);
|
||
</pre>
|
||
<pre>MULPD __m128d _mm_mul_pd (__m128d a, __m128d b);
|
||
</pre>
|
||
<h2 class="exceptions" id="simd-floating-point-exceptions">SIMD Floating-Point Exceptions<a class="anchor" href="#simd-floating-point-exceptions">
|
||
¶
|
||
</a></h2>
|
||
<p>Overflow, Underflow, Invalid, Precision, Denormal.</p>
|
||
<h2 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
|
||
¶
|
||
</a></h2>
|
||
<p>Non-EVEX-encoded instruction, see <span class="not-imported">Table 2-19</span>, “Type 2 Class Exception Conditions.”</p>
|
||
<p>EVEX-encoded instruction, see <span class="not-imported">Table 2-46</span>, “Type E2 Class Exception Conditions.”</p><footer><p>
|
||
This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
|
||
inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
|
||
ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
|
||
</p></footer></body></html>
|