forked from NRZCode/ia32-64
111 lines
3.9 KiB
HTML
111 lines
3.9 KiB
HTML
<!DOCTYPE html>
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>KADDW/KADDB/KADDQ/KADDD
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— ADD Two Masks</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>KADDW/KADDB/KADDQ/KADDD
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— ADD Two Masks</h1>
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<table>
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<tr>
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<th>Opcode/Instruction</th>
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<th>Op/En</th>
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<th>64/32 bit Mode Support</th>
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<th>CPUID Feature Flag</th>
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<th>Description</th></tr>
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<tr>
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<td>VEX.L1.0F.W0 4A /r KADDW k1, k2, k3</td>
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<td>RVR</td>
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<td>V/V</td>
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<td>AVX512DQ</td>
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<td>Add 16 bits masks in k2 and k3 and place result in k1.</td></tr>
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<tr>
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<td>VEX.L1.66.0F.W0 4A /r KADDB k1, k2, k3</td>
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<td>RVR</td>
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<td>V/V</td>
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<td>AVX512DQ</td>
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<td>Add 8 bits masks in k2 and k3 and place result in k1.</td></tr>
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<tr>
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<td>VEX.L1.0F.W1 4A /r KADDQ k1, k2, k3</td>
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<td>RVR</td>
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<td>V/V</td>
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<td>AVX512BW</td>
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<td>Add 64 bits masks in k2 and k3 and place result in k1.</td></tr>
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<tr>
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<td>VEX.L1.66.0F.W1 4A /r KADDD k1, k2, k3</td>
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<td>RVR</td>
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<td>V/V</td>
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<td>AVX512BW</td>
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<td>Add 32 bits masks in k2 and k3 and place result in k1.</td></tr></table>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Operand 3</th></tr>
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<tr>
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<td>RVR</td>
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<td>ModRM:reg (w)</td>
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<td>VEX.1vvv (r)</td>
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<td>ModRM:r/m (r, ModRM:[7:6] must be 11b)</td></tr></table>
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<h2 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h2>
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<p>Adds the vector mask k2 and the vector mask k3, and writes the result into vector mask k1.</p>
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<h2 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h2>
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<h3 id="kaddw">KADDW<a class="anchor" href="#kaddw">
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¶
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</a></h3>
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<pre>DEST[15:0] := SRC1[15:0] + SRC2[15:0]
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DEST[MAX_KL-1:16] := 0
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</pre>
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<h3 id="kaddb">KADDB<a class="anchor" href="#kaddb">
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¶
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</a></h3>
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<pre>DEST[7:0] := SRC1[7:0] + SRC2[7:0]
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DEST[MAX_KL-1:8] := 0
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</pre>
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<h3 id="kaddq">KADDQ<a class="anchor" href="#kaddq">
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¶
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</a></h3>
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<pre>DEST[63:0] := SRC1[63:0] + SRC2[63:0]
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DEST[MAX_KL-1:64] := 0
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</pre>
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<h3 id="kaddd">KADDD<a class="anchor" href="#kaddd">
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¶
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</a></h3>
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<pre>DEST[31:0] := SRC1[31:0] + SRC2[31:0]
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DEST[MAX_KL-1:32] := 0
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</pre>
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<h2 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
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¶
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</a></h2>
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<pre>KADDW __mmask16 _kadd_mask16 (__mmask16 a, __mmask16 b);
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</pre>
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<pre>KADDB __mmask8 _kadd_mask8 (__mmask8 a, __mmask8 b);
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</pre>
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<pre>KADDQ __mmask64 _kadd_mask64 (__mmask64 a, __mmask64 b);
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</pre>
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<pre>KADDD __mmask32 _kadd_mask32 (__mmask32 a, __mmask32 b);
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</pre>
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<h2 id="flags-affected">Flags Affected<a class="anchor" href="#flags-affected">
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¶
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</a></h2>
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<p>None.</p>
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<h2 class="exceptions" id="simd-floating-point-exceptions">SIMD Floating-Point Exceptions<a class="anchor" href="#simd-floating-point-exceptions">
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¶
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</a></h2>
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<p>None.</p>
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<h2 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
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¶
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</a></h2>
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<p>See <span class="not-imported">Table 2-63</span>, “TYPE K20 Exception Definition (VEX-Encoded OpMask Instructions w/o Memory Arg).”</p><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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