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5.3 KiB
HTML
132 lines
5.3 KiB
HTML
<!DOCTYPE html>
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>FLD1/FLDL2T/FLDL2E/FLDPI/FLDLG2/FLDLN2/FLDZ
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— Load Constant</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>FLD1/FLDL2T/FLDL2E/FLDPI/FLDLG2/FLDLN2/FLDZ
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— Load Constant</h1>
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<table>
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<tr>
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<th>Opcode*</th>
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<th>Instruction</th>
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<th>64-Bit Mode</th>
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<th>Compat/Leg Mode</th>
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<th>Description</th></tr>
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<tr>
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<td>D9 E8</td>
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<td>FLD1</td>
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<td>Valid</td>
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<td>Valid</td>
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<td>Push +1.0 onto the FPU register stack.</td></tr>
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<tr>
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<td>D9 E9</td>
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<td>FLDL2T</td>
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<td>Valid</td>
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<td>Valid</td>
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<td>Push log<sub>2</sub>10 onto the FPU register stack.</td></tr>
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<tr>
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<td>D9 EA</td>
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<td>FLDL2E</td>
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<td>Valid</td>
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<td>Valid</td>
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<td>Push log<sub>2</sub>e onto the FPU register stack.</td></tr>
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<tr>
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<td>D9 EB</td>
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<td>FLDPI</td>
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<td>Valid</td>
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<td>Valid</td>
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<td>Push π onto the FPU register stack.</td></tr>
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<tr>
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<td>D9 EC</td>
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<td>FLDLG2</td>
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<td>Valid</td>
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<td>Valid</td>
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<td>Push log<sub>10</sub>2 onto the FPU register stack.</td></tr>
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<tr>
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<td>D9 ED</td>
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<td>FLDLN2</td>
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<td>Valid</td>
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<td>Valid</td>
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<td>Push log<sub>e</sub>2 onto the FPU register stack.</td></tr>
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<tr>
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<td>D9 EE</td>
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<td>FLDZ</td>
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<td>Valid</td>
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<td>Valid</td>
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<td>Push +0.0 onto the FPU register stack.</td></tr></table>
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<blockquote>
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<p>* SeeIA-32ArchitectureCompatibilitysectionbelow.</p></blockquote>
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<h2 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h2>
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<p>Push one of seven commonly used constants (in double extended-precision floating-point format) onto the FPU register stack. The constants that can be loaded with these instructions include +1.0, +0.0, log<sub>2</sub>10, log<sub>2</sub>e, π, log<sub>10</sub>2, and log<sub>e</sub>2. For each constant, an internal 66-bit constant is rounded (as specified by the RC field in the FPU control word) to double extended-precision floating-point format. The inexact-result exception (#P) is not generated as a result of the rounding, nor is the C1 flag set in the x87 FPU status word if the value is rounded up.</p>
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<p>See the section titled “Approximation of Pi” in Chapter 8 of the Intel<sup>®</sup> 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for a description of the π constant.</p>
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<p>This instruction’s operation is the same in non-64-bit modes and 64-bit mode.</p>
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<h2 id="ia-32-architecture-compatibility">IA-32 Architecture Compatibility<a class="anchor" href="#ia-32-architecture-compatibility">
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¶
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</a></h2>
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<p>When the RC field is set to round-to-nearest, the FPU produces the same constants that is produced by the Intel 8087 and Intel 287 math coprocessors.</p>
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<h2 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h2>
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<pre>TOP := TOP − 1;
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ST(0) := CONSTANT;
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</pre>
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<h2 id="fpu-flags-affected">FPU Flags Affected<a class="anchor" href="#fpu-flags-affected">
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¶
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</a></h2>
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<table>
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<tr>
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<td>C1</td>
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<td>Set to 1 if stack overflow occurred; otherwise, set to 0.</td></tr>
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<tr>
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<td>C0, C2, C3</td>
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<td>Undefined.</td></tr></table>
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<h2 class="exceptions" id="floating-point-exceptions">Floating-Point Exceptions<a class="anchor" href="#floating-point-exceptions">
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¶
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</a></h2>
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<table>
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<tr>
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<td>#IS</td>
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<td>Stack overflow occurred.</td></tr></table>
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<h2 class="exceptions" id="protected-mode-exceptions">Protected Mode Exceptions<a class="anchor" href="#protected-mode-exceptions">
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¶
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</a></h2>
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<table>
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<tr>
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<td>#NM</td>
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<td>CR0.EM[bit 2] or CR0.TS[bit 3] = 1.</td></tr>
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<tr>
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<td>#MF</td>
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<td>If there is a pending x87 FPU exception.</td></tr>
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<tr>
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<td>#UD</td>
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<td>If the LOCK prefix is used.</td></tr></table>
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<h2 class="exceptions" id="real-address-mode-exceptions">Real-Address Mode Exceptions<a class="anchor" href="#real-address-mode-exceptions">
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¶
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</a></h2>
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<p>Same exceptions as in protected mode.</p>
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<h2 class="exceptions" id="virtual-8086-mode-exceptions">Virtual-8086 Mode Exceptions<a class="anchor" href="#virtual-8086-mode-exceptions">
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¶
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</a></h2>
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<p>Same exceptions as in protected mode.</p>
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<h2 class="exceptions" id="virtual-8086-mode-exceptions">Virtual-8086 Mode Exceptions<a class="anchor" href="#virtual-8086-mode-exceptions">
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¶
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</a></h2>
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<p>Same exceptions as in protected mode.</p>
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<h2 class="exceptions" id="compatibility-mode-exceptions">Compatibility Mode Exceptions<a class="anchor" href="#compatibility-mode-exceptions">
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¶
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</a></h2>
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<p>Same exceptions as in protected mode.</p>
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<h2 class="exceptions" id="64-bit-mode-exceptions">64-Bit Mode Exceptions<a class="anchor" href="#64-bit-mode-exceptions">
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¶
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</a></h2>
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<p>Same exceptions as in protected mode.</p><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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