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<!DOCTYPE html>
<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>ETRACKC
— Activates EBLOCK Checks</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>ETRACKC
— Activates EBLOCK Checks</h1>
<table>
<tr>
<th>Opcode/Instruction</th>
<th>Op/En</th>
<th>64/32 bit Mode Support</th>
<th>CPUID Feature Flag</th>
<th>Description</th></tr>
<tr>
<td>EAX = 11H ENCLS[ETRACKC]</td>
<td>IR</td>
<td>V/V</td>
<td>EAX[6]</td>
<td>This leaf function activates EBLOCK checks.</td></tr></table>
<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
</a></h2>
<table>
<tr>
<td>Op/En</td>
<td colspan="2">EAX</td>
<td colspan="2">RCX</td></tr>
<tr>
<td>IR</td>
<td>ETRACK (In)</td>
<td>Return error code (Out)</td>
<td>Address of the destination EPC page (In, EA)</td>
<td>Address of the SECS page (In, EA)</td></tr></table>
<h3 id="description">Description<a class="anchor" href="#description">
</a></h3>
<p>The ETRACKC instruction is thread safe variant of ETRACK leaf and can be executed concurrently with other CPU threads operating on the same SECS.</p>
<p>This leaf function provides the mechanism for hardware to track that software has completed the required TLB address clears successfully. The instruction can only be executed when the current privilege level is 0.</p>
<p>The content of RCX is an effective address of an EPC page.</p>
<p>The table below provides additional information on the memory parameter of ETRACK leaf function.</p>
<h2 id="etrackc-memory-parameter-semantics">ETRACKC Memory Parameter Semantics<a class="anchor" href="#etrackc-memory-parameter-semantics">
</a></h2>
<table>
<tr>
<td>EPCPAGE</td></tr>
<tr>
<td>Read/Write access permitted by Enclave</td></tr></table>
<p>The error codes are:</p>
<figure id="tbl-38-48">
<table>
<tr>
<th>Error Code</th>
<th>Value</th>
<th>Description</th></tr>
<tr>
<td>No Error</td>
<td>0</td>
<td>ETRACKC successful.</td></tr>
<tr>
<td>SGX_EPC_PAGE_CONFLICT</td>
<td>7</td>
<td>Failure due to concurrent operation of another SGX instruction.</td></tr>
<tr>
<td>SGX_PG_INVLD</td>
<td>6</td>
<td>Target page is not a VALID EPC page.</td></tr>
<tr>
<td>SGX_PREV_TRK_INCMPL</td>
<td>17</td>
<td>All processors did not complete the previous tracking sequence.</td></tr>
<tr>
<td>SGX_TRACK_NOT_REQUIRED</td>
<td>27</td>
<td>Target page type does not require tracking.</td></tr></table>
<figcaption><span class="not-imported">Table 38-48</span>. ETRACKC Return Value in RAX</figcaption></figure>
<h3 id="concurrency-restrictions">Concurrency Restrictions<a class="anchor" href="#concurrency-restrictions">
</a></h3>
<figure id="tbl-38-49">
<table>
<tr>
<th rowspan="2">Leaf</th>
<th rowspan="2">Parameter</th>
<th colspan="3">Base Concurrency Restrictions</th></tr>
<tr>
<th>Access</th>
<th>On Conflict</th>
<th>SGX_CONFLICT VM Exit Qualification</th></tr>
<tr>
<td rowspan="2">ETRACKC</td>
<td>Target [DS:RCX]</td>
<td>Shared</td>
<td>SGX_EPC_PAGE_ CONFLICT</td>
<td></td></tr>
<tr>
<td>SECS implicit</td>
<td>Concurrent</td>
<td></td>
<td></td></tr></table>
<figcaption><span class="not-imported">Table 38-49</span>. Base Concurrency Restrictions of ETRACKC</figcaption></figure>
<figure id="tbl-38-50">
<table>
<tr>
<th rowspan="3">Leaf</th>
<th rowspan="3">Parameter</th>
<th colspan="6">Additional Concurrency Restrictions</th></tr>
<tr>
<th colspan="2">vs. EACCEPT, EACCEPTCOPY, EMODPE, EMODPR, EMODT</th>
<th colspan="2">vs. EADD, EEXTEND, EINIT</th>
<th colspan="2">vs. ETRACK, ETRACKC</th></tr>
<tr>
<th>Access</th>
<th>On Conflict</th>
<th>Access</th>
<th>On Conflict</th>
<th>Access</th>
<th>On Conflict</th></tr>
<tr>
<td rowspan="2">ETRACKC</td>
<td>Target [DS:RCX]</td>
<td>Concurrent</td>
<td></td>
<td>Concurrent</td>
<td></td>
<td>Concurrent</td>
<td></td></tr>
<tr>
<td>SECS implicit</td>
<td>Concurrent</td>
<td></td>
<td>Concurrent</td>
<td></td>
<td>Exclusive</td>
<td>SGX_EPC_PAGE _CONFLICT</td></tr></table>
<figcaption><span class="not-imported">Table 38-50</span>. Additional Concurrency Restrictions of ETRACKC</figcaption></figure>
<h3 id="operation">Operation<a class="anchor" href="#operation">
</a></h3>
<h2 id="temp-variables-in-etrackc-operational-flow">Temp Variables in ETRACKC Operational Flow<a class="anchor" href="#temp-variables-in-etrackc-operational-flow">
</a></h2>
<table>
<tr>
<th>Name</th>
<th>Type</th>
<th>Size (Bits)</th>
<th>Description</th></tr>
<tr>
<td>TMP_SECS</td>
<td>Physical Address</td>
<td>64</td>
<td>Physical address of the SECS of the page being modified.</td></tr></table>
<p>(* check alignment of EPCPAGE (RCX) *)</p>
<p>IF (DS:RCX is not 4KByte Aligned) THEN</p>
<p>#GP(0); FI;</p>
<p>(* check that EPCPAGE (DS:RCX) is the address of an EPC page *)</p>
<p>IF (DS:RCX does not resolve within an EPC) THEN</p>
<p>#PF(DS:RCX, PFEC.SGX); FI;</p>
<p>(* Check the EPC page for concurrency *)</p>
<p>IF (EPC page is being modified) THEN</p>
<p>RFLAGS.ZF := 1;</p>
<p>RFLAGS.CF := 0;</p>
<p>RAX := SGX_EPC_PAGE_CONFLICT;</p>
<p>goto DONE_POST_LOCK_RELEASE;</p>
<p>FI;</p>
<p>(* check to make sure the page is valid *)</p>
<p>IF (EPCM(DS:RCX).VALID = 0) THEN</p>
<p>RFLAGS.ZF := 1;</p>
<p>RFLAGS.CF := 0;</p>
<p>RAX := SGX_PG_INVLD;</p>
<p>GOTO DONE;</p>
<p>FI;</p>
<p>(* find out the target SECS page *)</p>
<p>IF (EPCM(DS:RCX).PT is PT_REG or PT_TCS or PT_TRIM or PT_SS_FIRST or PT_SS_REST) THEN</p>
<p>TMP_SECS := Obtain SECS through EPCM(DS:RCX).ENCLAVESECS;</p>
<p>ELSE IF (EPCM(DS:RCX).PT is PT_SECS) THEN</p>
<p>TMP_SECS := Obtain SECS through (DS:RCX);</p>
<p>ELSE</p>
<p>RFLAGS.ZF := 0;</p>
<p>RFLAGS.CF := 1;</p>
<p>RAX := SGX_TRACK_NOT_REQUIRED;</p>
<p>GOTO DONE;</p>
<p>FI;</p>
<p>(* Check concurrency with other Intel SGX instructions *)</p>
<p>IF (Other Intel SGX instructions using tracking facility on this SECS) THEN</p>
<p>IF ((VMX non-root mode) and</p>
<p>(ENABLE_EPC_VIRTUALIZATION_EXTENSIONS Execution Control = 1)) THEN</p>
<p>VMCS.Exit_reason := SGX_CONFLICT;</p>
<p>VMCS.Exit_qualification.code := TRACKING_RESOURCE_CONFLICT;</p>
<p>VMCS.Exit_qualification.error := 0;</p>
<p>VMCS.Guest-physical_address :=</p>
<p>SECS(TMP_SECS).ENCLAVECONTEXT;</p>
<p>VMCS.Guest-linear_address := 0;</p>
<p>Deliver VMEXIT;</p>
<p>FI;</p>
<p>RFLAGS.ZF := 1;</p>
<p>RFLAGS.CF := 0;</p>
<p>RAX := SGX_EPC_PAGE_CONFLICT;</p>
<p>GOTO DONE;</p>
<p>FI;</p>
<p>(* All processors must have completed the previous tracking cycle*)</p>
<p>IF ( (TMP_SECS).TRACKING ≠ 0) )</p>
<p>THEN</p>
<p>IF ((VMX non-root mode) and</p>
<p>(ENABLE_EPC_VIRTUALIZATION_EXTENSIONS Execution Control = 1)) THEN</p>
<p>VMCS.Exit_reason := SGX_CONFLICT;</p>
<p>VMCS.Exit_qualification.code := TRACKING_REFERENCE_CONFLICT;</p>
<p>VMCS.Exit_qualification.error := 0;</p>
<p>VMCS.Guest-physical_address :=</p>
<p>SECS(TMP_SECS).ENCLAVECONTEXT;</p>
<p>VMCS.Guest-linear_address := 0;</p>
<p>Deliver VMEXIT;</p>
<p>FI;</p>
<p>RFLAGS.ZF := 1;</p>
<p>RFLAGS.CF := 0;</p>
<p>RAX := SGX_PREV_TRK_INCMPL;</p>
<p>GOTO DONE;</p>
<p>FI;</p>
<p>RFLAGS.ZF := 0;</p>
<p>RFLAGS.CF := 0;</p>
<p>RAX := 0;</p>
<p>DONE:</p>
<p>(* clear flags *)</p>
<p>RFLAGS.PF,AF,OF,SF := 0;</p>
<h3 id="flags-affected">Flags Affected<a class="anchor" href="#flags-affected">
</a></h3>
<p>ZF is set if ETRACKC fails due to concurrent operations with another SGX instructions or target page is an invalid EPC page or tracking is not completed on SECS page; otherwise cleared.</p>
<p>CF is set if target page is not of a type that requires tracking; otherwise cleared.</p>
<p>PF, AF, OF, and SF are cleared.</p>
<h3 class="exceptions" id="protected-mode-exceptions">Protected Mode Exceptions<a class="anchor" href="#protected-mode-exceptions">
</a></h3>
<table>
<tr>
<td rowspan="3">#GP(0)</td>
<td>If the memory operand violates access-control policies of DS segment.</td></tr>
<tr>
<td>If DS segment is unusable.</td></tr>
<tr>
<td>If the memory operand is not properly aligned.</td></tr>
<tr>
<td rowspan="2">#PF(error</td>
<td>code) If the memory operand expected to be in EPC does not resolve to an EPC page.</td></tr>
<tr>
<td>If a page fault occurs in access memory operand.</td></tr></table>
<h3 class="exceptions" id="64-bit-mode-exceptions">64-Bit Mode Exceptions<a class="anchor" href="#64-bit-mode-exceptions">
</a></h3>
<table>
<tr>
<td rowspan="2">#GP(0)</td>
<td>If a memory address is in a non-canonical form.</td></tr>
<tr>
<td>If a memory operand is not properly aligned.</td></tr>
<tr>
<td rowspan="2">#PF(error</td>
<td>code) If the memory operand expected to be in EPC does not resolve to an EPC page.</td></tr>
<tr>
<td>If a page fault occurs in access memory operand.</td></tr></table><footer><p>
This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
</p></footer></body></html>
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