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197 lines
7 KiB
HTML
<!DOCTYPE html>
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>ETRACK
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— Activates EBLOCK Checks</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>ETRACK
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— Activates EBLOCK Checks</h1>
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<table>
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<tr>
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<th>Opcode/Instruction</th>
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<th>Op/En</th>
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<th>64/32 bit Mode Support</th>
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<th>CPUID Feature Flag</th>
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<th>Description</th></tr>
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<tr>
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<td>EAX = 0CH ENCLS[ETRACK]</td>
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<td>IR</td>
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<td>V/V</td>
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<td>SGX1</td>
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<td>This leaf function activates EBLOCK checks.</td></tr></table>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<td>Op/En</td>
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<td colspan="2">EAX</td>
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<td>RCX</td></tr>
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<tr>
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<td>IR</td>
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<td>ETRACK (In)</td>
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<td>Return error code (Out)</td>
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<td>Pointer to the SECS of the EPC page (In)</td></tr></table>
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<h3 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h3>
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<p>This leaf function provides the mechanism for hardware to track that software has completed the required TLB address clears successfully. The instruction can only be executed when the current privilege level is 0.</p>
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<p>The content of RCX is an effective address of an EPC page.</p>
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<p>The table below provides additional information on the memory parameter of ETRACK leaf function.</p>
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<h2 id="etrack-memory-parameter-semantics">ETRACK Memory Parameter Semantics<a class="anchor" href="#etrack-memory-parameter-semantics">
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¶
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</a></h2>
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<table>
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<tr>
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<td>EPCPAGE</td></tr>
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<tr>
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<td>Read/Write access permitted by Enclave</td></tr></table>
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<p>The error codes are:</p>
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<figure id="tbl-38-45">
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<table>
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<tr>
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<th>Error Code (see <span class="not-imported">Table 38-4</span>)</th>
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<th>Description</th></tr>
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<tr>
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<td>No Error</td>
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<td>ETRACK successful.</td></tr>
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<tr>
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<td>SGX_PREV_TRK_INCMPL</td>
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<td>All processors did not complete the previous shoot-down sequence.</td></tr></table>
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<figcaption><span class="not-imported">Table 38-45</span>. ETRACK Return Value in RAX</figcaption></figure>
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<h3 id="concurrency-restrictions">Concurrency Restrictions<a class="anchor" href="#concurrency-restrictions">
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¶
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</a></h3>
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<figure id="tbl-38-46">
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<table>
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<tr>
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<th rowspan="2">Leaf</th>
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<th rowspan="2">Parameter</th>
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<th colspan="3">Base Concurrency Restrictions</th></tr>
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<tr>
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<th></th>
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<th>On Conflict </th>
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<th></th></tr>
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<tr>
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<td>ETRACK ETRACK
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SECS [DS:RCX]
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Shared ETRACK
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SECS [DS:RCX]
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</td>
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<td>SECS [DS:RCX]</td>
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<td></td>
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<td></td>
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<td></td></tr></table>
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<figcaption><span class="not-imported">Table 38-46</span>. Base Concurrency Restrictions of ETRACK</figcaption></figure>
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<figure id="tbl-38-47">
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<table>
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<tr>
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<th rowspan="3">Leaf</th>
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<th rowspan="3">Parameter</th>
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<th colspan="6">Additional Concurrency Restrictions</th></tr>
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<tr>
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<th colspan="2">vs. EACCEPT, EACCEPTCOPY, EMODPE, EMODPR, EMODT</th>
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<th colspan="2">vs. EADD, EEXTEND, EINIT</th>
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<th colspan="2">vs. ETRACK, ETRACKC</th></tr>
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<tr>
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<th>Access</th>
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<th>On Conflict</th>
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<th>Access</th>
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<th>On Conflict</th>
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<th>Access</th>
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<th>On Conflict</th></tr>
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<tr>
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<td>ETRACK</td>
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<td>SECS [DS:RCX]</td>
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<td>Concurrent</td>
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<td></td>
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<td>Concurrent</td>
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<td></td>
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<td>Exclusive</td>
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<td>SGX_EPC_PAGE _CONFLICT</td></tr></table>
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<figcaption><span class="not-imported">Table 38-47</span>. Additional Concurrency Restrictions of ETRACK</figcaption></figure>
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<h3 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h3>
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<pre>IF (DS:RCX is not 4KByte Aligned)
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THEN #GP(0); FI;
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IF (DS:RCX does not resolve within an EPC)
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THEN #PF(DS:RCX); FI;
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(* Check concurrency with other Intel SGX instructions *)
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IF (Other Intel SGX instructions using tracking facility on this SECS)
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THEN
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IF (<<VMX non-root operation>> AND <<ENABLE_EPC_VIRTUALIZATION_EXTENSIONS>>)
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THEN
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VMCS.Exit_reason := SGX_CONFLICT;
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VMCS.Exit_qualification.code := TRACKING_RESOURCE_CONFLICT;
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VMCS.Exit_qualification.error := 0;
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VMCS.Guest-physical_address := SECS(TMP_SECS).ENCLAVECONTEXT;
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VMCS.Guest-linear_address := 0;
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Deliver VMEXIT;
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ELSE
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#GP(0);
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FI;
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FI;
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IF (EPCM(DS:RCX). VALID = 0)
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THEN #PF(DS:RCX); FI;
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IF (EPCM(DS:RCX).PT ≠ PT_SECS)
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THEN #PF(DS:RCX); FI;
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(* All processors must have completed the previous tracking cycle*)
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IF ( (DS:RCX).TRACKING ≠ 0) )
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THEN
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IF (<<VMX non-root operation>> AND <<ENABLE_EPC_VIRTUALIZATION_EXTENSIONS>>)
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THEN
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VMCS.Exit_reason := SGX_CONFLICT;
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VMCS.Exit_qualification.code := TRACKING_REFERENCE_CONFLICT;
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VMCS.Exit_qualification.error := 0;
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VMCS.Guest-physical_address := SECS(TMP_SECS).ENCLAVECONTEXT;
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VMCS.Guest-linear_address := 0;
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Deliver VMEXIT;
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FI;
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RFLAGS.ZF := 1;
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RAX := SGX_PREV_TRK_INCMPL;
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GOTO DONE;
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ELSE
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RAX := 0;
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RFLAGS.ZF := 0;
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FI;
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DONE:
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RFLAGS.CF,PF,AF,OF,SF := 0;
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</pre>
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<h3 id="flags-affected">Flags Affected<a class="anchor" href="#flags-affected">
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¶
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</a></h3>
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<p>Sets ZF if SECS is in use or invalid, otherwise cleared. Clears CF, PF, AF, OF, SF.</p>
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<h3 class="exceptions" id="protected-mode-exceptions">Protected Mode Exceptions<a class="anchor" href="#protected-mode-exceptions">
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¶
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</a></h3>
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<table>
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<tr>
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<td rowspan="3">#GP(0)</td>
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<td>If a memory operand effective address is outside the DS segment limit.</td></tr>
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<tr>
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<td>If a memory operand is not properly aligned.</td></tr>
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<tr>
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<td>If another thread is concurrently using the tracking facility on this SECS.</td></tr>
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<tr>
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<td rowspan="2">#PF(error</td>
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<td>code) If a page fault occurs in accessing memory operands.</td></tr>
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<tr>
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<td>If a memory operand is not an EPC page.</td></tr></table>
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<h3 class="exceptions" id="64-bit-mode-exceptions">64-Bit Mode Exceptions<a class="anchor" href="#64-bit-mode-exceptions">
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¶
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</a></h3>
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<table>
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<tr>
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<td rowspan="3">#GP(0)</td>
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<td>If a memory operand is non-canonical form.</td></tr>
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<tr>
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<td>If a memory operand is not properly aligned.</td></tr>
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<tr>
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<td>If the specified EPC resource is in use.</td></tr>
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<tr>
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<td rowspan="2">#PF(error</td>
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<td>code) If a page fault occurs in accessing memory operands.</td></tr>
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<tr>
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<td>If a memory operand is not an EPC page.</td></tr></table><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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