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263 lines
10 KiB
HTML
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>EEXTEND
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— Extend Uninitialized Enclave Measurement by 256 Bytes</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>EEXTEND
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— Extend Uninitialized Enclave Measurement by 256 Bytes</h1>
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<table>
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<tr>
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<th>Opcode/Instruction</th>
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<th>Op/En</th>
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<th>64/32 bit Mode Support</th>
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<th>CPUID Feature Flag</th>
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<th>Description</th></tr>
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<tr>
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<td>EAX = 06H ENCLS[EEXTEND]</td>
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<td>IR</td>
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<td>V/V</td>
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<td>SGX1</td>
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<td>This leaf function measures 256 bytes of an uninitialized enclave page.</td></tr></table>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<td>Op/En</td>
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<td>EAX</td>
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<td>EBX</td>
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<td>RCX</td></tr>
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<tr>
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<td>IR</td>
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<td>EEXTEND (In)</td>
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<td>Effective address of the SECS of the data chunk (In)</td>
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<td>Effective address of a 256-byte chunk in the EPC (In)</td></tr></table>
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<h3 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h3>
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<p>This leaf function updates the MRENCLAVE measurement register of an SECS with the measurement of an EXTEND string compromising of “EEXTEND” || ENCLAVEOFFSET || PADDING || 256 bytes of the enclave page. This instruction can only be executed when current privilege level is 0 and the enclave is uninitialized.</p>
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<p>RBX contains the effective address of the SECS of the region to be measured. The address must be the same as the one used to add the page into the enclave.</p>
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<p>RCX contains the effective address of the 256 byte region of an EPC page to be measured. The DS segment is used to create linear addresses. Segment override is not supported.</p>
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<h2 id="eextend-memory-parameter-semantics">EEXTEND Memory Parameter Semantics<a class="anchor" href="#eextend-memory-parameter-semantics">
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¶
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</a></h2>
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<table>
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<tr>
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<td>EPC[RCX]</td></tr>
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<tr>
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<td>Read access by Enclave</td></tr></table>
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<p>The instruction faults if any of the following:</p>
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<h2 id="eextend-faulting-conditions">EEXTEND Faulting Conditions<a class="anchor" href="#eextend-faulting-conditions">
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¶
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</a></h2>
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<table>
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<tr>
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<td>RBX points to an address not 4KBytes aligned.</td>
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<td>RBX does not resolve to an SECS.</td></tr>
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<tr>
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<td>RBX does not point to an SECS page.</td>
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<td>RBX does not point to the SECS page of the data chunk.</td></tr>
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<tr>
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<td>RCX points to an address not 256B aligned.</td>
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<td>RCX points to an unused page or a SECS.</td></tr>
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<tr>
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<td>RCX does not resolve in an EPC page.</td>
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<td>If SECS is locked.</td></tr>
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<tr>
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<td>If the SECS is already initialized.</td>
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<td>May page fault.</td></tr>
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<tr>
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<td>CPL > 0.</td>
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<td></td></tr></table>
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<h3 id="concurrency-restrictions">Concurrency Restrictions<a class="anchor" href="#concurrency-restrictions">
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¶
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</a></h3>
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<figure id="tbl-38-23">
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<table>
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<tr>
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<th rowspan="2">Leaf</th>
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<th rowspan="2">Parameter</th>
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<th colspan="3">Base Concurrency Restrictions</th></tr>
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<tr>
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<th>Access</th>
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<th>On Conflict</th>
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<th>SGX_CONFLICT VM Exit Qualification</th></tr>
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<tr>
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<td rowspan="2">EEXTEND</td>
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<td>Target [DS:RCX]</td>
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<td>Shared</td>
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<td>#GP</td>
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<td></td></tr>
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<tr>
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<td>SECS [DS:RBX]</td>
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<td>Concurrent</td>
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<td></td>
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<td></td></tr></table>
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<figcaption><span class="not-imported">Table 38-23</span>. Base Concurrency Restrictions of EEXTEND</figcaption></figure>
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<figure id="tbl-38-24">
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<table>
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<tr>
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<th rowspan="3">Leaf</th>
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<th rowspan="3">Parameter</th>
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<th colspan="6">Additional Concurrency Restrictions</th></tr>
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<tr>
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<th colspan="2">vs. EACCEPT, EACCEPTCOPY, EMODPE, EMODPR, EMODT</th>
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<th colspan="2">vs. EADD, EEXTEND, EINIT</th>
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<th colspan="2">vs. ETRACK, ETRACKC</th></tr>
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<tr>
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<th>Access</th>
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<th>On Conflict</th>
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<th>Access</th>
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<th>On Conflict</th>
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<th>Access</th>
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<th>On Conflict</th></tr>
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<tr>
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<td rowspan="2">EEXTEND</td>
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<td>Target [DS:RCX]</td>
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<td>Concurrent</td>
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<td></td>
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<td>Concurrent</td>
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<td></td>
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<td>Concurrent</td>
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<td></td></tr>
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<tr>
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<td>SECS [DS:RBX]</td>
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<td>Concurrent</td>
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<td></td>
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<td>Exclusive</td>
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<td>#GP</td>
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<td>Concurrent</td>
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<td></td></tr></table>
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<figcaption><span class="not-imported">Table 38-24</span>. Additional Concurrency Restrictions of EEXTEND</figcaption></figure>
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<h3 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h3>
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<h2 id="temp-variables-in-eextend-operational-flow">Temp Variables in EEXTEND Operational Flow<a class="anchor" href="#temp-variables-in-eextend-operational-flow">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Name</th>
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<th>Type</th>
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<th>Size (Bits)</th>
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<th>Description</th></tr>
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<tr>
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<td>TMP_SECS</td>
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<td></td>
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<td>64</td>
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<td>Physical address of SECS of the enclave to which source operand belongs.</td></tr>
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<tr>
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<td>TMP_ENCLAVEOFFS ET</td>
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<td>Enclave Offset</td>
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<td>64</td>
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<td>The page displacement from the enclave base address.</td></tr>
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<tr>
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<td>TMPUPDATEFIELD</td>
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<td>SHA256 Buffer</td>
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<td>512</td>
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<td>Buffer used to hold data being added to TMP_SECS.MRENCLAVE.</td></tr></table>
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<p>TMP_MODE64 := ((IA32_EFER.LMA = 1) && (CS.L = 1));</p>
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<p>IF (DS:RBX is not 4096 Byte Aligned)</p>
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<p>THEN #GP(0); FI;</p>
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<p>IF (DS:RBX does not resolve to an EPC page)</p>
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<p>THEN #PF(DS:RBX); FI;</p>
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<p>IF (DS:RCX is not 256Byte Aligned)</p>
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<p>THEN #GP(0); FI;</p>
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<p>IF (DS:RCX does not resolve within an EPC)</p>
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<p>THEN #PF(DS:RCX); FI;</p>
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<p>(* make sure no other Intel SGX instruction is accessing EPCM *)</p>
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<p>IF (Other instructions accessing EPCM)</p>
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<p>THEN #GP(0); FI;</p>
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<p>IF (EPCM(DS:RCX). VALID = 0)</p>
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<p>THEN #PF(DS:RCX); FI;</p>
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<p>(* make sure that DS:RCX (DST) is pointing to a PT_REG or PT_TCS or PT_SS_FIRST or PT_SS_REST *)</p>
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<p>IF ( (EPCM(DS:RCX).PT ≠ PT_REG) and (EPCM(DS:RCX).PT ≠ PT_TCS)</p>
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<p>and (EPCM(DS:RCX).PT ≠ PT_SS_FIRST) and (EPCM(DS:RCX).PT ≠ PT_SS_REST))</p>
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<p>THEN #PF(DS:RCX); FI;</p>
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<p>TMP_SECS := Get_SECS_ADDRESS();</p>
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<p>IF (DS:RBX does not resolve to TMP_SECS)</p>
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<p>THEN #GP(0); FI;</p>
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<p>(* make sure no other instruction is accessing MRENCLAVE or ATTRIBUTES.INIT *)</p>
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<p>IF ( (Other instruction accessing MRENCLAVE) or (Other instructions checking or updating the initialized state of the SECS))</p>
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<p>THEN #GP(0); FI;</p>
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<p>(* Calculate enclave offset *)</p>
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<p>TMP_ENCLAVEOFFSET := EPCM(DS:RCX).ENCLAVEADDRESS - TMP_SECS.BASEADDR;</p>
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<p>TMP_ENCLAVEOFFSET := TMP_ENCLAVEOFFSET + (DS:RCX & 0FFFH)</p>
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<p>(* Add EEXTEND message and offset to MRENCLAVE *)</p>
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<p>TMPUPDATEFIELD[63:0] := 00444E4554584545H; // “EEXTEND”</p>
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<p>TMPUPDATEFIELD[127:64] := TMP_ENCLAVEOFFSET;</p>
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<p>TMPUPDATEFIELD[511:128] := 0; // 48 bytes</p>
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<p>TMP_SECS.MRENCLAVE := SHA256UPDATE(TMP_SECS.MRENCLAVE, TMPUPDATEFIELD)</p>
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<p>INC enclave’s MRENCLAVE update counter;</p>
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<p>(*Add 256 bytes to MRENCLAVE, 64 byte at a time *)</p>
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<p>TMP_SECS.MRENCLAVE := SHA256UPDATE(TMP_SECS.MRENCLAVE, DS:RCX[511:0] );</p>
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<p>TMP_SECS.MRENCLAVE := SHA256UPDATE(TMP_SECS.MRENCLAVE, DS:RCX[1023: 512] );</p>
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<p>TMP_SECS.MRENCLAVE := SHA256UPDATE(TMP_SECS.MRENCLAVE, DS:RCX[1535: 1024] );</p>
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<p>TMP_SECS.MRENCLAVE := SHA256UPDATE(TMP_SECS.MRENCLAVE, DS:RCX[2047: 1536] );</p>
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<p>INC enclave’s MRENCLAVE update counter by 4;</p>
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<h3 id="flags-affected">Flags Affected<a class="anchor" href="#flags-affected">
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¶
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</a></h3>
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<p>None</p>
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<h3 class="exceptions" id="protected-mode-exceptions">Protected Mode Exceptions<a class="anchor" href="#protected-mode-exceptions">
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¶
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</a></h3>
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<table>
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<tr>
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<td rowspan="7">#GP(0)</td>
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<td>If the address in RBX is outside the DS segment limit.</td></tr>
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<tr>
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<td>If RBX points to an SECS page which is not the SECS of the data chunk.</td></tr>
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<tr>
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<td>If the address in RCX is outside the DS segment limit.</td></tr>
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<tr>
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<td>If RCX points to a memory location not 256Byte-aligned.</td></tr>
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<tr>
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<td>If another instruction is accessing MRENCLAVE.</td></tr>
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<tr>
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<td>If another instruction is checking or updating the SECS.</td></tr>
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<tr>
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<td>If the enclave is already initialized.</td></tr>
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<tr>
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<td rowspan="5">#PF(error</td>
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<td>code) If a page fault occurs in accessing memory operands.</td></tr>
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<tr>
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<td>If the address in RBX points to a non-EPC page.</td></tr>
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<tr>
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<td>If the address in RCX points to a page which is not PT_TCS or PT_REG.</td></tr>
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<tr>
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<td>If the address in RCX points to a non-EPC page.</td></tr>
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<tr>
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<td>If the address in RCX points to an invalid EPC page.</td></tr></table>
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<h3 class="exceptions" id="64-bit-mode-exceptions">64-Bit Mode Exceptions<a class="anchor" href="#64-bit-mode-exceptions">
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¶
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</a></h3>
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<table>
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<tr>
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<td rowspan="7">#GP(0)</td>
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<td>If RBX is non-canonical form.</td></tr>
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<tr>
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<td>If RBX points to an SECS page which is not the SECS of the data chunk.</td></tr>
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<tr>
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<td>If RCX is non-canonical form.</td></tr>
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<tr>
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<td>If RCX points to a memory location not 256 Byte-aligned.</td></tr>
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<tr>
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<td>If another instruction is accessing MRENCLAVE.</td></tr>
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<tr>
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<td>If another instruction is checking or updating the SECS.</td></tr>
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<tr>
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<td>If the enclave is already initialized.</td></tr>
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<tr>
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<td rowspan="5">#PF(error</td>
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<td>code) If a page fault occurs in accessing memory operands.</td></tr>
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<tr>
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<td>If the address in RBX points to a non-EPC page.</td></tr>
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<tr>
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<td>If the address in RCX points to a page which is not PT_TCS or PT_REG.</td></tr>
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<tr>
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<td>If the address in RCX points to a non-EPC page.</td></tr>
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<tr>
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<td>If the address in RCX points to an invalid EPC page.</td></tr></table><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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