forked from NRZCode/ia32-64
344 lines
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HTML
344 lines
14 KiB
HTML
<!DOCTYPE html>
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>ECREATE
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— Create an SECS page in the Enclave Page Cache</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>ECREATE
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— Create an SECS page in the Enclave Page Cache</h1>
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<table>
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<tr>
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<th>Opcode/Instruction</th>
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<th>Op/En</th>
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<th>64/32 bit Mode Support</th>
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<th>CPUID Feature Flag</th>
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<th>Description</th></tr>
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<tr>
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<td>EAX = 00H ENCLS[ECREATE]</td>
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<td>IR</td>
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<td>V/V</td>
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<td>SGX1</td>
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<td>This leaf function begins an enclave build by creating an SECS page in EPC.</td></tr></table>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<td>Op/En</td>
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<td>EAX</td>
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<td>RBX</td>
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<td>RCX</td></tr>
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<tr>
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<td>IR</td>
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<td>ECREATE (In)</td>
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<td>Address of a PAGEINFO (In)</td>
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<td>Address of the destination SECS page (In)</td></tr></table>
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<h3 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h3>
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<p>ENCLS[ECREATE] is the first instruction executed in the enclave build process. ECREATE copies an SECS structure outside the EPC into an SECS page inside the EPC. The internal structure of SECS is not accessible to software.</p>
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<p>ECREATE will set up fields in the protected SECS and mark the page as valid inside the EPC. ECREATE initializes or checks unused fields.</p>
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<p>Software sets the following fields in the source structure: SECS:BASEADDR, SECS:SIZE in bytes, ATTRIBUTES, CONFIGID, and CONFIGSVN. SECS:BASEADDR must be naturally aligned on an SECS.SIZE boundary. SECS.SIZE must be at least 2 pages (8192).</p>
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<p>The source operand RBX contains an effective address of a PAGEINFO structure. PAGEINFO contains an effective address of a source SECS and an effective address of an SECINFO. The SECS field in PAGEINFO is not used.</p>
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<p>The RCX register is the effective address of the destination SECS. It is an address of an empty slot in the EPC. The SECS structure must be page aligned. SECINFO flags must specify the page as an SECS page.</p>
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<h2 id="ecreate-memory-parameter-semantics">ECREATE Memory Parameter Semantics<a class="anchor" href="#ecreate-memory-parameter-semantics">
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¶
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</a></h2>
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<table>
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<tr>
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<td>PAGEINFO</td>
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<td>PAGEINFO.SRCPGE</td>
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<td>PAGEINFO.SECINFO</td>
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<td>EPCPAGE</td></tr>
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<tr>
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<td>Read access permitted by Non Enclave</td>
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<td>Read access permitted by Non Enclave</td>
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<td>Read access permitted by Non Enclave</td>
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<td>Write access permitted by Enclave</td></tr></table>
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<p>ECREATE will fault if the SECS target page is in use; already valid; outside the EPC. It will also fault if addresses are not aligned; unused PAGEINFO fields are not zero.</p>
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<p>If the amount of space needed to store the SSA frame is greater than the amount specified in SECS.SSAFRAMESIZE, a #GP(0) results. The amount of space needed for an SSA frame is computed based on DS:TMP_SECS.ATTRIBUTES.XFRM size. Details of computing the size can be found Section 39.7.</p>
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<h3 id="concurrency-restrictions">Concurrency Restrictions<a class="anchor" href="#concurrency-restrictions">
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¶
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</a></h3>
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<figure id="tbl-38-15">
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<table>
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<tr>
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<th rowspan="2">Leaf</th>
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<th rowspan="2">Parameter</th>
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<th colspan="3">Base Concurrency Restrictions</th></tr>
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<tr>
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<th></th>
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<th>On Conflict </th>
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<th></th></tr>
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<tr>
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<td>ECREATE ECREATE
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SECS [DS:RCX]
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Exclusive #GP ECREATE
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SECS [DS:RCX]
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</td>
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<td>SECS [DS:RCX]</td>
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<td></td>
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<td></td>
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<td></td></tr></table>
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<figcaption><span class="not-imported">Table 38-15</span>. Base Concurrency Restrictions of ECREATE</figcaption></figure>
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<figure id="tbl-38-16">
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<table>
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<tr>
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<th rowspan="3">Leaf</th>
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<th rowspan="3">Parameter</th>
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<th colspan="6">Additional Concurrency Restrictions</th></tr>
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<tr>
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<th colspan="2">vs. EACCEPT, EACCEPTCOPY, vs. EADD, EEXTEND, EINIT
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vs. ETRACK, ETRACKC
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Access vs. ETRACK, ETRACKC
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Access On Conflict
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Access vs. ETRACK, ETRACKC
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Access On Conflict
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EMODPE, EMODPR, EMODT</th>
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<th colspan="2">vs. EADD, EEXTEND, EINIT vs. EADD, EEXTEND, EINIT
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vs. ETRACK, ETRACKC
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</th>
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<th colspan="2">vs. ETRACK, ETRACKC</th></tr>
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<tr>
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<th>Access On Conflict
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Access On Conflict
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Access Access On Conflict
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Access On Conflict
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</th>
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<th></th>
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<th></th>
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<th></th>
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<th></th>
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<th></th></tr>
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<tr>
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<td>ECREATE</td>
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<td>SECS [DS:RCX]</td>
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<td>Concurrent</td>
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<td></td>
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<td>Concurrent</td>
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<td></td>
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<td>Concurrent</td>
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<td></td></tr></table>
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<figcaption><span class="not-imported">Table 38-16</span>. Additional Concurrency Restrictions of ECREATE</figcaption></figure>
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<h3 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h3>
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<h2 id="temp-variables-in-ecreate-operational-flow">Temp Variables in ECREATE Operational Flow<a class="anchor" href="#temp-variables-in-ecreate-operational-flow">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Name</th>
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<th>Type</th>
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<th>Size (Bits)</th>
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<th>Description</th></tr>
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<tr>
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<td>TMP_SRCPGE</td>
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<td>Effective Address</td>
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<td>32/64</td>
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<td>Effective address of the SECS source page.</td></tr>
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<tr>
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<td>TMP_SECS</td>
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<td>Effective Address</td>
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<td>32/64</td>
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<td>Effective address of the SECS destination page.</td></tr>
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<tr>
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<td>TMP_SECINFO</td>
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<td>Effective Address</td>
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<td>32/64</td>
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<td>Effective address of an SECINFO structure which contains security attributes of the SECS page to be added.</td></tr>
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<tr>
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<td>TMP_XSIZE</td>
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<td>SSA Size</td>
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<td>64</td>
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<td>The size calculation of SSA frame.</td></tr>
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<tr>
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<td>TMP_MISC_SIZE</td>
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<td>MISC Field Size</td>
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<td>64</td>
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<td>Size of the selected MISC field components.</td></tr>
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<tr>
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<td>TMPUPDATEFIELD</td>
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<td>SHA256 Buffer</td>
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<td>512</td>
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<td>Buffer used to hold data being added to TMP_SECS.MRENCLAVE.</td></tr></table>
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<p>IF (DS:RBX is not 32Byte Aligned)</p>
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<p>THEN #GP(0); FI;</p>
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<p>IF (DS:RCX is not 4KByte Aligned)</p>
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<p>THEN #GP(0); FI;</p>
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<p>IF (DS:RCX does not resolve within an EPC)</p>
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<p>THEN #PF(DS:RCX); FI;</p>
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<p>TMP_SRCPGE := DS:RBX.SRCPGE;</p>
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<p>TMP_SECINFO := DS:RBX.SECINFO;</p>
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<p>IF (DS:TMP_SRCPGE is not 4KByte aligned or DS:TMP_SECINFO is not 64Byte aligned)</p>
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<p>THEN #GP(0); FI;</p>
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<p>IF (DS:RBX.LINADDR ! = 0 or DS:RBX.SECS ≠ 0)</p>
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<p>THEN #GP(0); FI;</p>
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<p>(* Check for misconfigured SECINFO flags*)</p>
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<p>IF (DS:TMP_SECINFO reserved fields are not zero or DS:TMP_SECINFO.FLAGS.PT ≠ PT_SECS)</p>
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<p>THEN #GP(0); FI;</p>
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<p>TMP_SECS := RCX;</p>
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<p>IF (EPC entry in use)</p>
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<p>THEN</p>
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<p>IF (<<VMX non-root operation>> AND <<ENABLE_EPC_VIRTUALIZATION_EXTENSIONS>>)</p>
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<p>THEN</p>
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<p>VMCS.Exit_reason := SGX_CONFLICT;</p>
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<p>VMCS.Exit_qualification.code := EPC_PAGE_CONFLICT_EXCEPTION;</p>
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<p>VMCS.Exit_qualification.error := 0;</p>
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<p>VMCS.Guest-physical_address :=</p>
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<p><< translation of DS:TMP_SECS produced by paging >>;</p>
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<p>VMCS.Guest-linear_address := DS:TMP_SECS;</p>
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<p>Deliver VMEXIT;</p>
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<p>ELSE</p>
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<p>#GP(0);</p>
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<p>FI;</p>
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<p>FI;</p>
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<p>IF (EPC entry in use)</p>
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<p>THEN #GP(0); FI;</p>
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<p>IF (EPCM(DS:RCX).VALID = 1)</p>
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<p>THEN #PF(DS:RCX); FI;</p>
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<p>(* Copy 4KBytes from source page to EPC page*)</p>
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<p>DS:RCX[32767:0] := DS:TMP_SRCPGE[32767:0];</p>
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<p>(* Check lower 2 bits of XFRM are set *)</p>
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<p>IF ( ( DS:TMP_SECS.ATTRIBUTES.XFRM BitwiseAND 03H) ≠ 03H)</p>
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<p>THEN #GP(0); FI;</p>
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<p>IF (XFRM is illegal)</p>
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<p>THEN #GP(0); FI;</p>
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<p>(* Check legality of CET_ATTRIBUTES *)</p>
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<p>IF ((DS:TMP_SECS.ATTRIBUTES.CET = 0 and DS:TMP_SECS.CET_ATTRIBUTES ≠ 0) ||</p>
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<p>(DS:TMP_SECS.ATTRIBUTES.CET = 0 and DS:TMP_SECS.CET_LEG_BITMAP_OFFSET ≠ 0) ||</p>
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<p>(CPUID.(EAX=7, ECX=0):EDX[CET_IBT] = 0 and DS:TMP_SECS.CET_LEG_BITMAP_OFFSET ≠ 0) ||</p>
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<p>(CPUID.(EAX=7, ECX=0):EDX[CET_IBT] = 0 and DS:TMP_SECS.CET_ATTRIBUTES[5:2] ≠ 0) ||</p>
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<p>(CPUID.(EAX=7, ECX=0):ECX[CET_SS] = 0 and DS:TMP_SECS.CET_ATTRIBUTES[1:0] ≠ 0) ||</p>
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<p>(DS:TMP_SECS.ATTRIBUTES.MODE64BIT = 1 and</p>
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<p>(DS:TMP_SECS.BASEADDR + DS:TMP_SECS.CET_LEG_BITMAP_OFFSET) not canonical) ||</p>
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<p>(DS:TMP_SECS.ATTRIBUTES.MODE64BIT = 0 and</p>
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<p>(DS:TMP_SECS.BASEADDR + DS:TMP_SECS.CET_LEG_BITMAP_OFFSET) & 0xFFFFFFFF00000000) ||</p>
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<p>(DS:TMP_SECS.CET_ATTRIBUTES.reserved fields not 0) or</p>
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<p>(DS:TMP_SECS.CET_LEG_BITMAP_OFFSET) is not page aligned))</p>
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<p>THEN</p>
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<p>#GP(0);</p>
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<p>FI;</p>
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<p>(* Make sure that the SECS does not have any unsupported MISCSELECT options*)</p>
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<p>IF ( !(CPUID.(EAX=12H, ECX=0):EBX[31:0] & DS:TMP_SECS.MISCSELECT[31:0]) )</p>
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<p>THEN</p>
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<p>EPCM(DS:TMP_SECS).EntryLock.Release();</p>
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<p>#GP(0);</p>
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<p>FI;</p>
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<p>( * Compute size of MISC area *)</p>
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<p>TMP_MISC_SIZE := compute_misc_region_size();</p>
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<p>(* Compute the size required to save state of the enclave on async exit, see Section 39.7.2.2*)</p>
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<p>TMP_XSIZE := compute_xsave_size(DS:TMP_SECS.ATTRIBUTES.XFRM) + GPR_SIZE + TMP_MISC_SIZE;</p>
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<p>(* Ensure that the declared area is large enough to hold XSAVE and GPR stat *)</p>
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<p>IF ( DS:TMP_SECS.SSAFRAMESIZE*4096 < TMP_XSIZE)</p>
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<p>THEN #GP(0); FI;</p>
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<p>IF ( (DS:TMP_SECS.ATTRIBUTES.MODE64BIT = 1) and (DS:TMP_SECS.BASEADDR is not canonical) )</p>
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<p>THEN #GP(0); FI;</p>
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<p>IF ( (DS:TMP_SECS.ATTRIBUTES.MODE64BIT = 0) and (DS:TMP_SECS.BASEADDR and 0FFFFFFFF00000000H) )</p>
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<p>THEN #GP(0); FI;</p>
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<p>IF ( (DS:TMP_SECS.ATTRIBUTES.MODE64BIT = 0) and (DS:TMP_SECS.SIZE ≥ 2 ^ (CPUID.(EAX=12H, ECX=0):.EDX[7:0]) ) ) THEN #GP(0); FI;</p>
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<p>IF ( (DS:TMP_SECS.ATTRIBUTES.MODE64BIT = 1) and (DS:TMP_SECS.SIZE ≥ 2 ^ (CPUID.(EAX=12H, ECX=0):.EDX[15:8]) ) ) THEN #GP(0); FI;</p>
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<p>(* Enclave size must be at least 8192 bytes and must be power of 2 in bytes*)</p>
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<p>IF (DS:TMP_SECS.SIZE < 8192 or popcnt(DS:TMP_SECS.SIZE) > 1)</p>
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<p>THEN #GP(0); FI;</p>
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<p>(* Ensure base address of an enclave is aligned on size*)</p>
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<p>IF ( ( DS:TMP_SECS.BASEADDR and (DS:TMP_SECS.SIZE-1) ) )</p>
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<p>THEN #GP(0); FI;</p>
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<p>(* Ensure the SECS does not have any unsupported attributes*)</p>
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<p>IF ( DS:TMP_SECS.ATTRIBUTES and (~CR_SGX_ATTRIBUTES_MASK) )</p>
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<p>THEN #GP(0); FI;</p>
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<p>IF ( DS:TMP_SECS reserved fields are not zero)</p>
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<p>THEN #GP(0); FI;</p>
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<p>(* Verify that CONFIGID/CONFIGSVN are not set with attribute *)</p>
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<p>IF ( ((DS:TMP_SECS.CONFIGID ≠ 0) or (DS:TMP_SECS.CONFIGSVN ≠0)) AND (DS:TMP_SECS.ATTRIBUTES.KSS == 0 ))</p>
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<p>THEN #GP(0); FI;</p>
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<p>Clear DS:TMP_SECS to Uninitialized;</p>
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<p>DS:TMP_SECS.MRENCLAVE := SHA256INITIALIZE(DS:TMP_SECS.MRENCLAVE);</p>
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<p>DS:TMP_SECS.ISVSVN := 0;</p>
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<p>DS:TMP_SECS.ISVPRODID := 0;</p>
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<p>(* Initialize hash updates etc*)</p>
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<p>Initialize enclave’s MRENCLAVE update counter;</p>
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<p>(* Add “ECREATE” string and SECS fields to MRENCLAVE *)</p>
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<p>TMPUPDATEFIELD[63:0] := 0045544145524345H; // “ECREATE”</p>
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<p>TMPUPDATEFIELD[95:64] := DS:TMP_SECS.SSAFRAMESIZE;</p>
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<p>TMPUPDATEFIELD[159:96] := DS:TMP_SECS.SIZE;</p>
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<p>IF (CPUID.(EAX=7, ECX=0):EDX[CET_IBT] = 1)</p>
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<p>THEN</p>
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<p>TMPUPDATEFIELD[223:160] := DS:TMP_SECS.CET_LEG_BITMAP_OFFSET;</p>
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<p>ELSE</p>
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<p>TMPUPDATEFIELD[223:160] := 0;</p>
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<p>FI;</p>
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<p>TMPUPDATEFIELD[511:160] := 0;</p>
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<p>DS:TMP_SECS.MRENCLAVE := SHA256UPDATE(DS:TMP_SECS.MRENCLAVE, TMPUPDATEFIELD)</p>
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<p>INC enclave’s MRENCLAVE update counter;</p>
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<p>(* Set EID *)</p>
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<p>DS:TMP_SECS.EID := LockedXAdd(CR_NEXT_EID, 1);</p>
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<p>(* Initialize the virtual child count to zero *)</p>
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<p>DS:TMP_SECS.VIRTCHILDCNT := 0;</p>
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<p>(* Load ENCLAVECONTEXT with Address out of paging of SECS *)</p>
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<p><< store translation of DS:RCX produced by paging in SECS(DS:RCX).ENCLAVECONTEXT >></p>
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<p>(* Set the EPCM entry, first create SECS identifier and store the identifier in EPCM *)</p>
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<p>EPCM(DS:TMP_SECS).PT := PT_SECS;</p>
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<p>EPCM(DS:TMP_SECS).ENCLAVEADDRESS := 0;</p>
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<p>EPCM(DS:TMP_SECS).R := 0;</p>
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<p>EPCM(DS:TMP_SECS).W := 0;</p>
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<p>EPCM(DS:TMP_SECS).X := 0;</p>
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<p>(* Set EPCM entry fields *)</p>
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<p>EPCM(DS:RCX).BLOCKED := 0;</p>
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<p>EPCM(DS:RCX).PENDING := 0;</p>
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<p>EPCM(DS:RCX).MODIFIED := 0;</p>
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<p>EPCM(DS:RCX).PR := 0;</p>
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<p>EPCM(DS:RCX).VALID := 1;</p>
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<h3 id="flags-affected">Flags Affected<a class="anchor" href="#flags-affected">
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¶
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</a></h3>
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<p>None</p>
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<h3 class="exceptions" id="protected-mode-exceptions">Protected Mode Exceptions<a class="anchor" href="#protected-mode-exceptions">
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¶
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</a></h3>
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<table>
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<tr>
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<td rowspan="7">#GP(0)</td>
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<td>If a memory operand effective address is outside the DS segment limit.</td></tr>
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<tr>
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<td>If a memory operand is not properly aligned.</td></tr>
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<tr>
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<td>If the reserved fields are not zero.</td></tr>
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<tr>
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<td>If PAGEINFO.SECS is not zero.</td></tr>
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<tr>
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<td>If PAGEINFO.LINADDR is not zero.</td></tr>
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<tr>
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<td>If the SECS destination is locked.</td></tr>
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<tr>
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<td>If SECS.SSAFRAMESIZE is insufficient.</td></tr>
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<tr>
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<td rowspan="2">#PF(error</td>
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<td>code) If a page fault occurs in accessing memory operands.</td></tr>
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<tr>
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<td>If the SECS destination is outside the EPC.</td></tr></table>
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<h3 class="exceptions" id="64-bit-mode-exceptions">64-Bit Mode Exceptions<a class="anchor" href="#64-bit-mode-exceptions">
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¶
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</a></h3>
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<table>
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<tr>
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<td rowspan="7">#GP(0)</td>
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<td>If a memory address is non-canonical form.</td></tr>
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<tr>
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<td>If a memory operand is not properly aligned.</td></tr>
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<tr>
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<td>If the reserved fields are not zero.</td></tr>
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<tr>
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<td>If PAGEINFO.SECS is not zero.</td></tr>
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<tr>
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<td>If PAGEINFO.LINADDR is not zero.</td></tr>
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<tr>
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<td>If the SECS destination is locked.</td></tr>
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<tr>
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<td>If SECS.SSAFRAMESIZE is insufficient.</td></tr>
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<tr>
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<td rowspan="2">#PF(error</td>
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<td>code) If a page fault occurs in accessing memory operands.</td></tr>
|
||
<tr>
|
||
<td>If the SECS destination is outside the EPC.</td></tr></table><footer><p>
|
||
This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
|
||
inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
|
||
ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
|
||
</p></footer></body></html>
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