forked from NRZCode/ia32-64
81 lines
3.6 KiB
HTML
81 lines
3.6 KiB
HTML
<!DOCTYPE html>
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>BLSMSK
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— Get Mask Up to Lowest Set Bit</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>BLSMSK
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— Get Mask Up to Lowest Set Bit</h1>
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<table>
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<tr>
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<th>Opcode/Instruction</th>
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<th>Op/En</th>
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<th>64/32-bit Mode</th>
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<th>CPUID Feature Flag</th>
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<th>Description</th></tr>
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<tr>
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<td>VEX.LZ.0F38.W0 F3 /2 BLSMSK r32, r/m32</td>
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<td>VM</td>
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<td>V/V</td>
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<td>BMI1</td>
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<td>Set all lower bits in r32 to “1” starting from bit 0 to lowest set bit in r/m32.</td></tr>
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<tr>
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<td>VEX.LZ.0F38.W1 F3 /2 BLSMSK r64, r/m64</td>
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<td>VM</td>
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<td>V/N.E.</td>
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<td>BMI1</td>
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<td>Set all lower bits in r64 to “1” starting from bit 0 to lowest set bit in r/m64.</td></tr></table>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Operand 3</th>
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<th>Operand 4</th></tr>
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<tr>
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<td>VM</td>
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<td>VEX.vvvv (w)</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td>
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<td>N/A</td></tr></table>
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<h2 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h2>
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<p>Sets all the lower bits of the destination operand to “1” up to and including lowest set bit (=1) in the source operand. If source operand is zero, BLSMSK sets all bits of the destination operand to 1 and also sets CF to 1.</p>
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<p>This instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in 64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An attempt to execute this instruction with VEX.L not equal to 0 will cause #UD.</p>
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<h2 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h2>
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<pre>temp := (SRC-1) XOR (SRC) ;
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SF := temp[OperandSize -1];
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ZF := 0;
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IF SRC = 0
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CF := 1;
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ELSE
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CF := 0;
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FI
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DEST := temp;
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</pre>
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<h2 id="flags-affected">Flags Affected<a class="anchor" href="#flags-affected">
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¶
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</a></h2>
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<p>SF is updated based on the result. CF is set if the source if zero. ZF and OF flags are cleared. AF and PF flag are undefined.</p>
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<h2 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
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¶
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</a></h2>
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<pre>BLSMSK unsigned __int32 _blsmsk_u32(unsigned __int32 src);
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</pre>
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<pre>BLSMSK unsigned __int64 _blsmsk_u64(unsigned __int64 src);
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</pre>
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<h2 class="exceptions" id="simd-floating-point-exceptions">SIMD Floating-Point Exceptions<a class="anchor" href="#simd-floating-point-exceptions">
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¶
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</a></h2>
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<p>None.</p>
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<h2 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
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¶
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</a></h2>
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<p>See <span class="not-imported">Table 2-29</span>, “Type 13 Class Exception Conditions.”</p><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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