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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>AESKEYGENASSIST
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— AES Round Key Generation Assist</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>AESKEYGENASSIST
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— AES Round Key Generation Assist</h1>
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<table>
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<tr>
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<th>Opcode/Instruction</th>
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<th>Op/En</th>
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<th>64/32-bit Mode</th>
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<th>CPUID Feature Flag</th>
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<th>Description</th></tr>
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<tr>
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<td>66 0F 3A DF /r ib AESKEYGENASSIST xmm1, xmm2/m128, imm8</td>
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<td>RMI</td>
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<td>V/V</td>
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<td>AES</td>
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<td>Assist in AES round key generation using an 8 bits Round Constant (RCON) specified in the immediate byte, operating on 128 bits of data specified in xmm2/m128 and stores the result in xmm1.</td></tr>
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<tr>
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<td>VEX.128.66.0F3A.WIG DF /r ib VAESKEYGENASSIST xmm1, xmm2/m128, imm8</td>
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<td>RMI</td>
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<td>V/V</td>
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<td>Both AES and AVX flags</td>
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<td>Assist in AES round key generation using 8 bits Round Constant (RCON) specified in the immediate byte, operating on 128 bits of data specified in xmm2/m128 and stores the result in xmm1.</td></tr></table>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Operand 3</th>
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<th>Operand 4</th></tr>
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<tr>
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<td>RMI</td>
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<td>ModRM:reg (w)</td>
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<td>ModRM:r/m (r)</td>
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<td>imm8</td>
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<td>N/A</td></tr></table>
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<h2 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h2>
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<p>Assist in expanding the AES cipher key, by computing steps towards generating a round key for encryption, using 128-bit data specified in the source operand and an 8-bit round constant specified as an immediate, store the result in the destination operand.</p>
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<p>The destination operand is an XMM register. The source operand can be an XMM register or a 128-bit memory location.</p>
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<p>128-bit Legacy SSE version: Bits (MAXVL-1:128) of the corresponding YMM destination register remain unchanged.</p>
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<p>VEX.128 encoded version: Bits (MAXVL-1:128) of the destination YMM register are zeroed.</p>
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<p>Note: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.</p>
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<h2 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h2>
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<h3 id="aeskeygenassist">AESKEYGENASSIST<a class="anchor" href="#aeskeygenassist">
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¶
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</a></h3>
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<pre>X3[31:0] := SRC [127: 96];
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X2[31:0] := SRC [95: 64];
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X1[31:0] := SRC [63: 32];
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X0[31:0] := SRC [31: 0];
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RCON[31:0] := ZeroExtend(imm8[7:0]);
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DEST[31:0] := SubWord(X1);
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DEST[63:32 ] := RotWord( SubWord(X1) ) XOR RCON;
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DEST[95:64] := SubWord(X3);
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DEST[127:96] := RotWord( SubWord(X3) ) XOR RCON;
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DEST[MAXVL-1:128] (Unmodified)
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</pre>
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<h3 id="vaeskeygenassist">VAESKEYGENASSIST<a class="anchor" href="#vaeskeygenassist">
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¶
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</a></h3>
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<pre>X3[31:0] := SRC [127: 96];
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X2[31:0] := SRC [95: 64];
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X1[31:0] := SRC [63: 32];
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X0[31:0] := SRC [31: 0];
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RCON[31:0] := ZeroExtend(imm8[7:0]);
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DEST[31:0] := SubWord(X1);
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DEST[63:32 ] := RotWord( SubWord(X1) ) XOR RCON;
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DEST[95:64] := SubWord(X3);
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DEST[127:96] := RotWord( SubWord(X3) ) XOR RCON;
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DEST[MAXVL-1:128] := 0;
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</pre>
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<h2 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
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¶
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</a></h2>
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<pre>(V)AESKEYGENASSIST __m128i _mm_aeskeygenassist (__m128i, const int)
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</pre>
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<h2 class="exceptions" id="simd-floating-point-exceptions">SIMD Floating-Point Exceptions<a class="anchor" href="#simd-floating-point-exceptions">
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¶
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</a></h2>
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<p>None.</p>
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<h2 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
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¶
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</a></h2>
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<p>See <span class="not-imported">Table 2-21</span>, “Type 4 Class Exception Conditions,” additionally:</p>
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<table>
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<tr>
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<td>#UD</td>
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<td>If VEX.vvvv ≠ 1111B.</td></tr></table><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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