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166 lines
13 KiB
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<!DOCTYPE html>
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>ADDSUBPS
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— Packed Single Precision Floating-Point Add/Subtract</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>ADDSUBPS
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— Packed Single Precision Floating-Point Add/Subtract</h1>
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<table>
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<tr>
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<th>Opcode/Instruction</th>
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<th>Op/En</th>
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<th>64/32-bit Mode</th>
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<th>CPUID Feature Flag</th>
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<th>Description</th></tr>
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<tr>
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<td>F2 0F D0 /r ADDSUBPS xmm1, xmm2/m128</td>
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<td>RM</td>
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<td>V/V</td>
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<td>SSE3</td>
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<td>Add/subtract single precision floating-point values from xmm2/m128 to xmm1.</td></tr>
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<tr>
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<td>VEX.128.F2.0F.WIG D0 /r VADDSUBPS xmm1, xmm2, xmm3/m128</td>
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<td>RVM</td>
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<td>V/V</td>
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<td>AVX</td>
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<td>Add/subtract single precision floating-point values from xmm3/mem to xmm2 and stores result in xmm1.</td></tr>
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<tr>
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<td>VEX.256.F2.0F.WIG D0 /r VADDSUBPS ymm1, ymm2, ymm3/m256</td>
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<td>RVM</td>
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<td>V/V</td>
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<td>AVX</td>
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<td>Add / subtract single precision floating-point values from ymm3/mem to ymm2 and stores result in ymm1.</td></tr></table>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Operand 3</th>
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<th>Operand 4</th></tr>
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<tr>
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<td>RM</td>
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<td>ModRM:reg (r, w)</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td>
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<td>N/A</td></tr>
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<tr>
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<td>RVM</td>
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<td>ModRM:reg (w)</td>
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<td>VEX.vvvv (r)</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td></tr></table>
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<h2 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h2>
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<p>Adds odd-numbered single precision floating-point values of the first source operand (second operand) with the corresponding single precision floating-point values from the second source operand (third operand); stores the result in the odd-numbered values of the destination operand (first operand). Subtracts the even-numbered single precision floating-point values from the second source operand from the corresponding single precision floating values in the first source operand; stores the result into the even-numbered values of the destination operand.</p>
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<p>In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to access additional registers (XMM8-XMM15).</p>
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<p>128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The destination is not distinct from the first source XMM register and the upper bits (MAXVL-1:128) of the corresponding YMM register destination are unmodified. See <a href='addsubps.html#fig-3-4'>Figure 3-4</a>.</p>
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<p>VEX.128 encoded version: the first source operand is an XMM register or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAXVL-1:128) of the corresponding YMM register destination are zeroed.</p>
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<p>VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM register or a 256-bit memory location. The destination operand is a YMM register.</p>
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<figure id="fig-3-4">
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.408277799999951pt; fill: #000" textLength="116.4683674000002" x="221.3897" y="18.14386300000001">ADDSUBPS xmm1, xmm2/m128</text>
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.408277799999951pt; fill: #000" textLength="24.00090000000006" x="437.07378785000003" y="38.65743223000004">xmm2/</text>
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.408277799999951pt; fill: #000" textLength="28.913084200000014" x="150.4017" y="43.456863">[127:96]</text>
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.408277799999951pt; fill: #000" textLength="24.46491740000002" x="229.135" y="43.456863">[95:64]</text>
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.408277799999951pt; fill: #000" textLength="24.464917400000047" x="305.6381" y="43.456863">[63:32]</text>
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.408277799999951pt; fill: #000" textLength="20.016750600000023" x="384.3613" y="43.456863">[31:0]</text>
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.408277799999951pt; fill: #000" textLength="20.008750300000088" x="437.07378785000003" y="48.257792230000064">m128</text>
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.408277799999951pt; fill: #000" textLength="32.30521139999996" x="437.07378785000003" y="92.65945723000004">RESULT:</text>
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.063515733038685pt; fill: #000" textLength="52.55836626360113" x="139.5214" y="92.58567721807572">xmm1[127:96] +</text>
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.063515733038685pt; fill: #000" textLength="70.42132331726216" x="207.3341" y="92.58567721807572">xmm1[95:64] - xmm2/</text>
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.063515733038685pt; fill: #000" textLength="48.51457826360098" x="294.4876" y="92.58567721807572">xmm1[63:32] +</text>
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.063515733038685pt; fill: #000" textLength="42.55616558866285" x="373.8308" y="92.58567721807572">xmm1[31:0] -</text>
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.408277799999951pt; fill: #000" textLength="21.776816600000075" x="437.07378785000003" y="102.25981723000007">xmm1</text>
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.063515733038685pt; fill: #000" textLength="66.39208131726227" x="132.7713287" y="102.18603721807574">xmm2/m128[127:96]</text>
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.063515733038685pt; fill: #000" textLength="40.52929331726219" x="221.7950059" y="102.18603721807574">m128[95:64]</text>
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.063515733038685pt; fill: #000" textLength="62.34829331726206" x="287.7375287" y="102.18603721807574">xmm2/m128[63:32]</text>
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.408277799999951pt; fill: #000" textLength="28.913084200000014" x="150.41210039" y="125.53514082000004">[127:96]</text>
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<figcaption><a href='addsubps.html#fig-3-4'>Figure 3-4</a>. ADDSUBPS—Packed Single Precision Floating-Point Add/Subtract</figcaption></figure>
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<h2 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h2>
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<h3 id="addsubps--128-bit-legacy-sse-version-">ADDSUBPS (128-bit Legacy SSE Version)<a class="anchor" href="#addsubps--128-bit-legacy-sse-version-">
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¶
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</a></h3>
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<pre>DEST[31:0] := DEST[31:0] - SRC[31:0]
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DEST[63:32] := DEST[63:32] + SRC[63:32]
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DEST[95:64] := DEST[95:64] - SRC[95:64]
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DEST[127:96] := DEST[127:96] + SRC[127:96]
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DEST[MAXVL-1:128] (Unmodified)
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</pre>
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<h3 id="vaddsubps--vex-128-encoded-version-">VADDSUBPS (VEX.128 Encoded Version)<a class="anchor" href="#vaddsubps--vex-128-encoded-version-">
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¶
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</a></h3>
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<pre>DEST[31:0] := SRC1[31:0] - SRC2[31:0]
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DEST[63:32] := SRC1[63:32] + SRC2[63:32]
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DEST[95:64] := SRC1[95:64] - SRC2[95:64]
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DEST[127:96] := SRC1[127:96] + SRC2[127:96]
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DEST[MAXVL-1:128] := 0
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</pre>
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<h3 id="vaddsubps--vex-256-encoded-version-">VADDSUBPS (VEX.256 Encoded Version)<a class="anchor" href="#vaddsubps--vex-256-encoded-version-">
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¶
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</a></h3>
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<pre>DEST[31:0] := SRC1[31:0] - SRC2[31:0]
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DEST[63:32] := SRC1[63:32] + SRC2[63:32]
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DEST[95:64] := SRC1[95:64] - SRC2[95:64]
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DEST[127:96] := SRC1[127:96] + SRC2[127:96]
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DEST[159:128] := SRC1[159:128] - SRC2[159:128]
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DEST[191:160] := SRC1[191:160] + SRC2[191:160]
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DEST[223:192] := SRC1[223:192] - SRC2[223:192]
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DEST[255:224] := SRC1[255:224] + SRC2[255:224]
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</pre>
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<h2 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
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¶
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</a></h2>
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<pre>ADDSUBPS __m128 _mm_addsub_ps(__m128 a, __m128 b)
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</pre>
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<pre>VADDSUBPS __m256 _mm256_addsub_ps (__m256 a, __m256 b)
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</pre>
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<h2 class="exceptions" id="exceptions">Exceptions<a class="anchor" href="#exceptions">
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¶
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</a></h2>
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<p>When the source operand is a memory operand, the operand must be aligned on a 16-byte boundary or a general-protection exception (#GP) will be generated.</p>
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<h2 class="exceptions" id="simd-floating-point-exceptions">SIMD Floating-Point Exceptions<a class="anchor" href="#simd-floating-point-exceptions">
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¶
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</a></h2>
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<p>Overflow, Underflow, Invalid, Precision, Denormal.</p>
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<h2 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
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¶
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</a></h2>
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<p>See <span class="not-imported">Table 2-19</span>, “Type 2 Class Exception Conditions.”</p><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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