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160 lines
7.3 KiB
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>ADCX
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— Unsigned Integer Addition of Two Operands With Carry Flag</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>ADCX
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— Unsigned Integer Addition of Two Operands With Carry Flag</h1>
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<table>
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<tr>
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<th>Opcode/Instruction</th>
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<th>Op/En</th>
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<th>64/32bit Mode Support</th>
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<th>CPUID Feature Flag</th>
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<th>Description</th></tr>
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<tr>
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<td>66 0F 38 F6 /r ADCX r32, r/m32</td>
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<td>RM</td>
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<td>V/V</td>
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<td>ADX</td>
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<td>Unsigned addition of r32 with CF, r/m32 to r32, writes CF.</td></tr>
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<tr>
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<td>66 REX.w 0F 38 F6 /r ADCX r64, r/m64</td>
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<td>RM</td>
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<td>V/N.E.</td>
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<td>ADX</td>
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<td>Unsigned addition of r64 with CF, r/m64 to r64, writes CF.</td></tr></table>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Operand 3</th>
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<th>Operand 4</th></tr>
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<tr>
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<td>RM</td>
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<td>ModRM:reg (r, w)</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td>
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<td>N/A</td></tr></table>
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<h2 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h2>
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<p>Performs an unsigned addition of the destination operand (first operand), the source operand (second operand) and the carry-flag (CF) and stores the result in the destination operand. The destination operand is a general-purpose register, whereas the source operand can be a general-purpose register or memory location. The state of CF can represent a carry from a previous addition. The instruction sets the CF flag with the carry generated by the unsigned addition of the operands.</p>
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<p>The ADCX instruction is executed in the context of multi-precision addition, where we add a series of operands with a carry-chain. At the beginning of a chain of additions, we need to make sure the CF is in a desired initial state. Often, this initial state needs to be 0, which can be achieved with an instruction to zero the CF (e.g. XOR).</p>
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<p>This instruction is supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in 64-bit mode.</p>
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<p>In 64-bit mode, the default operation size is 32 bits. Using a REX Prefix in the form of REX.R permits access to additional registers (R8-15). Using REX Prefix in the form of REX.W promotes operation to 64 bits.</p>
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<p>ADCX executes normally either inside or outside a transaction region.</p>
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<p>Note: ADCX defines the OF flag differently than the ADD/ADC instructions as defined in the Intel<sup>®</sup> 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A.</p>
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<h2 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h2>
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<pre>IF OperandSize is 64-bit
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THEN CF:DEST[63:0] := DEST[63:0] + SRC[63:0] + CF;
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ELSE CF:DEST[31:0] := DEST[31:0] + SRC[31:0] + CF;
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FI;
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</pre>
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<h2 id="flags-affected">Flags Affected<a class="anchor" href="#flags-affected">
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¶
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</a></h2>
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<p>CF is updated based on result. OF, SF, ZF, AF, and PF flags are unmodified.</p>
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<h2 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
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¶
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</a></h2>
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<pre>unsigned char _addcarryx_u32 (unsigned char c_in, unsigned int src1, unsigned int src2, unsigned int *sum_out);
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</pre>
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<pre>unsigned char _addcarryx_u64 (unsigned char c_in, unsigned __int64 src1, unsigned __int64 src2, unsigned __int64 *sum_out);
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</pre>
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<h2 class="exceptions" id="simd-floating-point-exceptions">SIMD Floating-Point Exceptions<a class="anchor" href="#simd-floating-point-exceptions">
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¶
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</a></h2>
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<p>None.</p>
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<h2 class="exceptions" id="protected-mode-exceptions">Protected Mode Exceptions<a class="anchor" href="#protected-mode-exceptions">
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¶
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</a></h2>
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<table>
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<tr>
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<td rowspan="2">#UD</td>
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<td>If the LOCK prefix is used.</td></tr>
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<tr>
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<td>If CPUID.(EAX=07H, ECX=0H):EBX.ADX[bit 19] = 0.</td></tr>
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<tr>
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<td>#SS(0)</td>
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<td>For an illegal address in the SS segment.</td></tr>
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<tr>
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<td rowspan="2">#GP(0)</td>
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<td>For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.</td></tr>
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<tr>
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<td>If the DS, ES, FS, or GS register is used to access memory and it contains a null segment selector.</td></tr>
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<tr>
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<td>#PF(fault-code)</td>
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<td>For a page fault.</td></tr>
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<tr>
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<td>#AC(0)</td>
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<td>If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.</td></tr></table>
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<h2 class="exceptions" id="real-address-mode-exceptions">Real-Address Mode Exceptions<a class="anchor" href="#real-address-mode-exceptions">
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¶
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</a></h2>
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<table>
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<tr>
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<td rowspan="2">#UD</td>
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<td>If the LOCK prefix is used.</td></tr>
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<tr>
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<td>If CPUID.(EAX=07H, ECX=0H):EBX.ADX[bit 19] = 0.</td></tr>
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<tr>
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<td>#SS(0)</td>
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<td>For an illegal address in the SS segment.</td></tr>
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<tr>
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<td>#GP(0)</td>
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<td>If any part of the operand lies outside the effective address space from 0 to FFFFH.</td></tr></table>
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<h2 class="exceptions" id="virtual-8086-mode-exceptions">Virtual-8086 Mode Exceptions<a class="anchor" href="#virtual-8086-mode-exceptions">
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¶
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</a></h2>
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<table>
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<tr>
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<td rowspan="2">#UD</td>
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<td>If the LOCK prefix is used.</td></tr>
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<tr>
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<td>If CPUID.(EAX=07H, ECX=0H):EBX.ADX[bit 19] = 0.</td></tr>
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<tr>
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<td>#SS(0)</td>
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<td>For an illegal address in the SS segment.</td></tr>
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<tr>
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<td>#GP(0)</td>
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<td>If any part of the operand lies outside the effective address space from 0 to FFFFH.</td></tr>
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<tr>
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<td>#PF(fault-code)</td>
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<td>For a page fault.</td></tr>
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<tr>
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<td>#AC(0)</td>
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<td>If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.</td></tr></table>
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<h2 class="exceptions" id="compatibility-mode-exceptions">Compatibility Mode Exceptions<a class="anchor" href="#compatibility-mode-exceptions">
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¶
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</a></h2>
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<p>Same exceptions as in protected mode.</p>
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<h2 class="exceptions" id="64-bit-mode-exceptions">64-Bit Mode Exceptions<a class="anchor" href="#64-bit-mode-exceptions">
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¶
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</a></h2>
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<table>
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<tr>
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<td rowspan="2">#UD</td>
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<td>If the LOCK prefix is used.</td></tr>
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<tr>
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<td>If CPUID.(EAX=07H, ECX=0H):EBX.ADX[bit 19] = 0.</td></tr>
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<tr>
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<td>#SS(0)</td>
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<td>If a memory address referencing the SS segment is in a non-canonical form.</td></tr>
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<tr>
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<td>#GP(0)</td>
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<td>If the memory address is in a non-canonical form.</td></tr>
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<tr>
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<td>#PF(fault-code)</td>
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<td>For a page fault.</td></tr>
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<tr>
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<td>#AC(0)</td>
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<td>If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.</td></tr></table><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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