forked from NRZCode/ia32-64
88 lines
3.9 KiB
HTML
88 lines
3.9 KiB
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>BSWAP
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— Byte Swap</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>BSWAP
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— Byte Swap</h1>
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<table>
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<tr>
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<th>Opcode</th>
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<th>Instruction</th>
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<th>Op/En</th>
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<th>64-bit Mode</th>
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<th>Compat/Leg Mode</th>
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<th>Description</th></tr>
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<tr>
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<td>0F C8+<em>rd</em></td>
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<td>BSWAP <em>r32</em></td>
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<td>O</td>
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<td>Valid*</td>
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<td>Valid</td>
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<td>Reverses the byte order of a 32-bit register.</td></tr>
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<tr>
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<td>REX.W + 0F C8+<em>rd</em></td>
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<td>BSWAP <em>r64</em></td>
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<td>O</td>
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<td>Valid</td>
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<td>N.E.</td>
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<td>Reverses the byte order of a 64-bit register.</td></tr></table>
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<blockquote>
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<p>* SeeIA-32ArchitectureCompatibilitysectionbelow.</p></blockquote>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Operand 3</th>
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<th>Operand 4</th></tr>
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<tr>
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<td>O</td>
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<td>opcode + rd (r, w)</td>
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<td>N/A</td>
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<td>N/A</td>
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<td>N/A</td></tr></table>
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<h2 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h2>
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<p>Reverses the byte order of a 32-bit or 64-bit (destination) register. This instruction is provided for converting little-endian values to big-endian format and vice versa. To swap bytes in a word value (16-bit register), use the XCHG instruction. When the BSWAP instruction references a 16-bit register, the result is undefined.</p>
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<p>In 64-bit mode, the instruction’s default operation size is 32 bits. Using a REX prefix in the form of REX.R permits access to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See the summary chart at the beginning of this section for encoding data and limits.</p>
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<h2 id="ia-32-architecture-legacy-compatibility">IA-32 Architecture Legacy Compatibility<a class="anchor" href="#ia-32-architecture-legacy-compatibility">
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¶
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</a></h2>
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<p>The BSWAP instruction is not supported on IA-32 processors earlier than the Intel486TM processor family. For compatibility with this instruction, software should include functionally equivalent code for execution on Intel processors earlier than the Intel486 processor family.</p>
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<h2 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h2>
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<pre>TEMP := DEST
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IF 64-bit mode AND OperandSize = 64
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THEN
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DEST[7:0] := TEMP[63:56];
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DEST[15:8] := TEMP[55:48];
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DEST[23:16] := TEMP[47:40];
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DEST[31:24] := TEMP[39:32];
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DEST[39:32] := TEMP[31:24];
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DEST[47:40] := TEMP[23:16];
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DEST[55:48] := TEMP[15:8];
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DEST[63:56] := TEMP[7:0];
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ELSE
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DEST[7:0] := TEMP[31:24];
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DEST[15:8] := TEMP[23:16];
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DEST[23:16] := TEMP[15:8];
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DEST[31:24] := TEMP[7:0];
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FI;
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</pre>
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<h2 id="flags-affected">Flags Affected<a class="anchor" href="#flags-affected">
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¶
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</a></h2>
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<p>None.</p>
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<h2 id="exceptions--all-operating-modes-">Exceptions (All Operating Modes)<a class="anchor" href="#exceptions--all-operating-modes-">
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¶
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</a></h2>
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<p>#UD If the LOCK prefix is used.</p><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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