forked from NRZCode/ia32-64
394 lines
15 KiB
HTML
394 lines
15 KiB
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>VEXTRACTF128/VEXTRACTF32x4/VEXTRACTF64x2/VEXTRACTF32x8/VEXTRACTF64x4
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— Extract Packed Floating-Point Values</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>VEXTRACTF128/VEXTRACTF32x4/VEXTRACTF64x2/VEXTRACTF32x8/VEXTRACTF64x4
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— Extract Packed Floating-Point Values</h1>
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<table>
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<tr>
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<th>Opcode/Instruction</th>
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<th>Op/En</th>
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<th>64/32 Bit Mode Support</th>
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<th>CPUID Feature Flag</th>
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<th>Description</th></tr>
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<tr>
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<td>VEX.256.66.0F3A.W0 19 /r ib VEXTRACTF128 xmm1/m128, ymm2, imm8</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX</td>
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<td>Extract 128 bits of packed floating-point values from ymm2 and store results in xmm1/m128.</td></tr>
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<tr>
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<td>EVEX.256.66.0F3A.W0 19 /r ib VEXTRACTF32X4 xmm1/m128 {k1}{z}, ymm2, imm8</td>
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<td>C</td>
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<td>V/V</td>
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<td>AVX512VL AVX512F</td>
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<td>Extract 128 bits of packed single precision floating-point values from ymm2 and store results in xmm1/m128 subject to writemask k1.</td></tr>
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<tr>
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<td>EVEX.512.66.0F3A.W0 19 /r ib VEXTRACTF32x4 xmm1/m128 {k1}{z}, zmm2, imm8</td>
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<td>C</td>
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<td>V/V</td>
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<td>AVX512F</td>
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<td>Extract 128 bits of packed single precision floating-point values from zmm2 and store results in xmm1/m128 subject to writemask k1.</td></tr>
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<tr>
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<td>EVEX.256.66.0F3A.W1 19 /r ib VEXTRACTF64X2 xmm1/m128 {k1}{z}, ymm2, imm8</td>
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<td>B</td>
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<td>V/V</td>
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<td>AVX512VL AVX512DQ</td>
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<td>Extract 128 bits of packed double precision floating-point values from ymm2 and store results in xmm1/m128 subject to writemask k1.</td></tr>
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<tr>
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<td>EVEX.512.66.0F3A.W1 19 /r ib VEXTRACTF64X2 xmm1/m128 {k1}{z}, zmm2, imm8</td>
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<td>B</td>
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<td>V/V</td>
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<td>AVX512DQ</td>
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<td>Extract 128 bits of packed double precision floating-point values from zmm2 and store results in xmm1/m128 subject to writemask k1.</td></tr>
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<tr>
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<td>EVEX.512.66.0F3A.W0 1B /r ib VEXTRACTF32X8 ymm1/m256 {k1}{z}, zmm2, imm8</td>
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<td>D</td>
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<td>V/V</td>
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<td>AVX512DQ</td>
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<td>Extract 256 bits of packed single precision floating-point values from zmm2 and store results in ymm1/m256 subject to writemask k1.</td></tr>
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<tr>
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<td>EVEX.512.66.0F3A.W1 1B /r ib VEXTRACTF64x4 ymm1/m256 {k1}{z}, zmm2, imm8</td>
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<td>C</td>
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<td>V/V</td>
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<td>AVX512F</td>
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<td>Extract 256 bits of packed double precision floating-point values from zmm2 and store results in ymm1/m256 subject to writemask k1.</td></tr></table>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Tuple Type</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Operand 3</th>
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<th>Operand 4</th></tr>
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<tr>
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<td>A</td>
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<td>N/A</td>
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<td>ModRM:r/m (w)</td>
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<td>ModRM:reg (r)</td>
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<td>imm8</td>
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<td>N/A</td></tr>
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<tr>
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<td>B</td>
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<td>Tuple2</td>
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<td>ModRM:r/m (w)</td>
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<td>ModRM:reg (r)</td>
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<td>imm8</td>
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<td>N/A</td></tr>
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<tr>
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<td>C</td>
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<td>Tuple4</td>
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<td>ModRM:r/m (w)</td>
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<td>ModRM:reg (r)</td>
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<td>imm8</td>
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<td>N/A</td></tr>
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<tr>
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<td>D</td>
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<td>Tuple8</td>
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<td>ModRM:r/m (w)</td>
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<td>ModRM:reg (r)</td>
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<td>imm8</td>
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<td>N/A</td></tr></table>
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<h3 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h3>
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<p>VEXTRACTF128/VEXTRACTF32x4 and VEXTRACTF64x2 extract 128-bits of single precision floating-point values from the source operand (the second operand) and store to the low 128-bit of the destination operand (the first operand). The 128-bit data extraction occurs at an 128-bit granular offset specified by imm8[0] (256-bit) or imm8[1:0] as the multiply factor. The destination may be either a vector register or an 128-bit memory location.</p>
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<p>VEXTRACTF32x4: The low 128-bit of the destination operand is updated at 32-bit granularity according to the writemask.</p>
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<p>VEXTRACTF32x8 and VEXTRACTF64x4 extract 256-bits of double precision floating-point values from the source operand (second operand) and store to the low 256-bit of the destination operand (the first operand). The 256-bit data extraction occurs at an 256-bit granular offset specified by imm8[0] (256-bit) or imm8[0] as the multiply factor The destination may be either a vector register or a 256-bit memory location.</p>
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<p>VEXTRACTF64x4: The low 256-bit of the destination operand is updated at 64-bit granularity according to the writemask.</p>
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<p>VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.</p>
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<p>The high 6 bits of the immediate are ignored.</p>
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<p>If VEXTRACTF128 is encoded with VEX.L= 0, an attempt to execute the instruction encoded with VEX.L= 0 will cause an #UD exception.</p>
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<h3 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h3>
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<h4 id="vextractf32x4--evex-encoded-versions--when-destination-is-a-register">VEXTRACTF32x4 (EVEX Encoded Versions) When Destination is a Register<a class="anchor" href="#vextractf32x4--evex-encoded-versions--when-destination-is-a-register">
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¶
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</a></h4>
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<pre>VL = 256, 512
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IF VL = 256
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CASE (imm8[0]) OF
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0: TMP_DEST[127:0] := SRC1[127:0]
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1: TMP_DEST[127:0] := SRC1[255:128]
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ESAC.
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FI;
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IF VL = 512
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CASE (imm8[1:0]) OF
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00: TMP_DEST[127:0] := SRC1[127:0]
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01: TMP_DEST[127:0] := SRC1[255:128]
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10: TMP_DEST[127:0] := SRC1[383:256]
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11: TMP_DEST[127:0] := SRC1[511:384]
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ESAC.
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FI;
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FOR j := 0 TO 3
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i := j * 32
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IF k1[j] OR *no writemask*
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THEN DEST[i+31:i] := TMP_DEST[i+31:i]
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ELSE
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IF *merging-masking*
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; merging-masking
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THEN *DEST[i+31:i] remains unchanged*
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ELSE *zeroing-masking*
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; zeroing-masking
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DEST[i+31:i] := 0
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FI
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FI;
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ENDFOR
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DEST[MAXVL-1:128] := 0
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</pre>
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<h4 id="vextractf32x4--evex-encoded-versions--when-destination-is-memory">VEXTRACTF32x4 (EVEX Encoded Versions) When Destination is Memory<a class="anchor" href="#vextractf32x4--evex-encoded-versions--when-destination-is-memory">
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¶
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</a></h4>
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<pre>VL = 256, 512
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IF VL = 256
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CASE (imm8[0]) OF
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0: TMP_DEST[127:0] := SRC1[127:0]
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1: TMP_DEST[127:0] := SRC1[255:128]
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ESAC.
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FI;
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IF VL = 512
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CASE (imm8[1:0]) OF
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00: TMP_DEST[127:0] := SRC1[127:0]
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01: TMP_DEST[127:0] := SRC1[255:128]
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10: TMP_DEST[127:0] := SRC1[383:256]
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11: TMP_DEST[127:0] := SRC1[511:384]
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ESAC.
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FI;
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FOR j := 0 TO 3
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i := j * 32
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IF k1[j] OR *no writemask*
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THEN DEST[i+31:i] := TMP_DEST[i+31:i]
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ELSE *DEST[i+31:i] remains unchanged* ; merging-masking
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FI;
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ENDFOR
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</pre>
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<h4 id="vextractf64x2--evex-encoded-versions--when-destination-is-a-register">VEXTRACTF64x2 (EVEX Encoded Versions) When Destination is a Register<a class="anchor" href="#vextractf64x2--evex-encoded-versions--when-destination-is-a-register">
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¶
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</a></h4>
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<pre>VL = 256, 512
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IF VL = 256
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CASE (imm8[0]) OF
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0: TMP_DEST[127:0] := SRC1[127:0]
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1: TMP_DEST[127:0] := SRC1[255:128]
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ESAC.
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FI;
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IF VL = 512
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CASE (imm8[1:0]) OF
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00: TMP_DEST[127:0] := SRC1[127:0]
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01: TMP_DEST[127:0] := SRC1[255:128]
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10: TMP_DEST[127:0] := SRC1[383:256]
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11: TMP_DEST[127:0] := SRC1[511:384]
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ESAC.
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FI;
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FOR j := 0 TO 1
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i := j * 64
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IF k1[j] OR *no writemask*
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THEN DEST[i+63:i] := TMP_DEST[i+63:i]
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ELSE
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IF *merging-masking*
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; merging-masking
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THEN *DEST[i+63:i] remains unchanged*
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ELSE *zeroing-masking*
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; zeroing-masking
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DEST[i+63:i] := 0
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FI
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FI;
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ENDFOR
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DEST[MAXVL-1:128] := 0
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</pre>
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<h4 id="vextractf64x2--evex-encoded-versions--when-destination-is-memory">VEXTRACTF64x2 (EVEX Encoded Versions) When Destination is Memory<a class="anchor" href="#vextractf64x2--evex-encoded-versions--when-destination-is-memory">
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¶
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</a></h4>
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<pre>VL = 256, 512
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IF VL = 256
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CASE (imm8[0]) OF
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0: TMP_DEST[127:0] := SRC1[127:0]
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1: TMP_DEST[127:0] := SRC1[255:128]
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ESAC.
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FI;
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IF VL = 512
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CASE (imm8[1:0]) OF
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00: TMP_DEST[127:0] := SRC1[127:0]
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01: TMP_DEST[127:0] := SRC1[255:128]
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10: TMP_DEST[127:0] := SRC1[383:256]
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11: TMP_DEST[127:0] := SRC1[511:384]
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ESAC.
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FI;
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FOR j := 0 TO 1
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i := j * 64
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IF k1[j] OR *no writemask*
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THEN DEST[i+63:i] := TMP_DEST[i+63:i]
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ELSE *DEST[i+63:i] remains unchanged*
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; merging-masking
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FI;
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ENDFOR
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</pre>
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<h4 id="vextractf32x8--evex-u1-512-encoded-version--when-destination-is-a-register">VEXTRACTF32x8 (EVEX.U1.512 Encoded Version) When Destination is a Register<a class="anchor" href="#vextractf32x8--evex-u1-512-encoded-version--when-destination-is-a-register">
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¶
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</a></h4>
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<pre>VL = 512
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CASE (imm8[0]) OF
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0: TMP_DEST[255:0] := SRC1[255:0]
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1: TMP_DEST[255:0] := SRC1[511:256]
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ESAC.
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FOR j := 0 TO 7
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i := j * 32
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IF k1[j] OR *no writemask*
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THEN DEST[i+31:i] := TMP_DEST[i+31:i]
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ELSE
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IF *merging-masking*
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; merging-masking
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THEN *DEST[i+31:i] remains unchanged*
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ELSE *zeroing-masking*
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; zeroing-masking
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DEST[i+31:i] := 0
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FI
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FI;
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ENDFOR
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DEST[MAXVL-1:256] := 0
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</pre>
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<h4 id="vextractf32x8--evex-u1-512-encoded-version--when-destination-is-memory">VEXTRACTF32x8 (EVEX.U1.512 Encoded Version) When Destination is Memory<a class="anchor" href="#vextractf32x8--evex-u1-512-encoded-version--when-destination-is-memory">
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¶
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</a></h4>
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<pre>CASE (imm8[0]) OF
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0: TMP_DEST[255:0] := SRC1[255:0]
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1: TMP_DEST[255:0] := SRC1[511:256]
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ESAC.
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FOR j := 0 TO 7
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i := j * 32
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IF k1[j] OR *no writemask*
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THEN DEST[i+31:i] := TMP_DEST[i+31:i]
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ELSE *DEST[i+31:i] remains unchanged*
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; merging-masking
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FI;
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ENDFOR
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</pre>
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<h4 id="vextractf64x4--evex-512-encoded-version--when-destination-is-a-register">VEXTRACTF64x4 (EVEX.512 Encoded Version) When Destination is a Register<a class="anchor" href="#vextractf64x4--evex-512-encoded-version--when-destination-is-a-register">
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¶
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</a></h4>
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<pre>VL = 512
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CASE (imm8[0]) OF
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|||
|
|
0: TMP_DEST[255:0] := SRC1[255:0]
|
|||
|
|
1: TMP_DEST[255:0] := SRC1[511:256]
|
|||
|
|
ESAC.
|
|||
|
|
FOR j := 0 TO 3
|
|||
|
|
i := j * 64
|
|||
|
|
IF k1[j] OR *no writemask*
|
|||
|
|
THEN DEST[i+63:i] := TMP_DEST[i+63:i]
|
|||
|
|
ELSE
|
|||
|
|
IF *merging-masking* ; merging-masking
|
|||
|
|
THEN *DEST[i+63:i] remains unchanged*
|
|||
|
|
ELSE *zeroing-masking*
|
|||
|
|
; zeroing-masking
|
|||
|
|
DEST[i+63:i] := 0
|
|||
|
|
FI
|
|||
|
|
FI;
|
|||
|
|
ENDFOR
|
|||
|
|
DEST[MAXVL-1:256] := 0
|
|||
|
|
</pre>
|
|||
|
|
<h4 id="vextractf64x4--evex-512-encoded-version--when-destination-is-memory">VEXTRACTF64x4 (EVEX.512 Encoded Version) When Destination is Memory<a class="anchor" href="#vextractf64x4--evex-512-encoded-version--when-destination-is-memory">
|
|||
|
|
¶
|
|||
|
|
</a></h4>
|
|||
|
|
<pre>CASE (imm8[0]) OF
|
|||
|
|
0: TMP_DEST[255:0] := SRC1[255:0]
|
|||
|
|
1: TMP_DEST[255:0] := SRC1[511:256]
|
|||
|
|
ESAC.
|
|||
|
|
FOR j := 0 TO 3
|
|||
|
|
i := j * 64
|
|||
|
|
IF k1[j] OR *no writemask*
|
|||
|
|
THEN DEST[i+63:i] := TMP_DEST[i+63:i]
|
|||
|
|
ELSE ; merging-masking
|
|||
|
|
*DEST[i+63:i] remains unchanged*
|
|||
|
|
FI;
|
|||
|
|
ENDFOR
|
|||
|
|
</pre>
|
|||
|
|
<h4 id="vextractf128--memory-destination-form-">VEXTRACTF128 (Memory Destination Form)<a class="anchor" href="#vextractf128--memory-destination-form-">
|
|||
|
|
¶
|
|||
|
|
</a></h4>
|
|||
|
|
<pre>CASE (imm8[0]) OF
|
|||
|
|
0: DEST[127:0] := SRC1[127:0]
|
|||
|
|
1: DEST[127:0] := SRC1[255:128]
|
|||
|
|
ESAC.
|
|||
|
|
</pre>
|
|||
|
|
<h4 id="vextractf128--register-destination-form-">VEXTRACTF128 (Register Destination Form)<a class="anchor" href="#vextractf128--register-destination-form-">
|
|||
|
|
¶
|
|||
|
|
</a></h4>
|
|||
|
|
<pre>CASE (imm8[0]) OF
|
|||
|
|
0: DEST[127:0] := SRC1[127:0]
|
|||
|
|
1: DEST[127:0] := SRC1[255:128]
|
|||
|
|
ESAC.
|
|||
|
|
DEST[MAXVL-1:128] := 0
|
|||
|
|
</pre>
|
|||
|
|
<h3 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
|
|||
|
|
¶
|
|||
|
|
</a></h3>
|
|||
|
|
<pre>VEXTRACTF32x4 __m128 _mm512_extractf32x4_ps(__m512 a, const int nidx);
|
|||
|
|
</pre>
|
|||
|
|
<pre>VEXTRACTF32x4 __m128 _mm512_mask_extractf32x4_ps(__m128 s, __mmask8 k, __m512 a, const int nidx);
|
|||
|
|
</pre>
|
|||
|
|
<pre>VEXTRACTF32x4 __m128 _mm512_maskz_extractf32x4_ps( __mmask8 k, __m512 a, const int nidx);
|
|||
|
|
</pre>
|
|||
|
|
<pre>VEXTRACTF32x4 __m128 _mm256_extractf32x4_ps(__m256 a, const int nidx);
|
|||
|
|
</pre>
|
|||
|
|
<pre>VEXTRACTF32x4 __m128 _mm256_mask_extractf32x4_ps(__m128 s, __mmask8 k, __m256 a, const int nidx);
|
|||
|
|
</pre>
|
|||
|
|
<pre>VEXTRACTF32x4 __m128 _mm256_maskz_extractf32x4_ps( __mmask8 k, __m256 a, const int nidx);
|
|||
|
|
</pre>
|
|||
|
|
<pre>VEXTRACTF32x8 __m256 _mm512_extractf32x8_ps(__m512 a, const int nidx);
|
|||
|
|
</pre>
|
|||
|
|
<pre>VEXTRACTF32x8 __m256 _mm512_mask_extractf32x8_ps(__m256 s, __mmask8 k, __m512 a, const int nidx);
|
|||
|
|
</pre>
|
|||
|
|
<pre>VEXTRACTF32x8 __m256 _mm512_maskz_extractf32x8_ps( __mmask8 k, __m512 a, const int nidx);
|
|||
|
|
</pre>
|
|||
|
|
<pre>VEXTRACTF64x2 __m128d _mm512_extractf64x2_pd(__m512d a, const int nidx);
|
|||
|
|
</pre>
|
|||
|
|
<pre>VEXTRACTF64x2 __m128d _mm512_mask_extractf64x2_pd(__m128d s, __mmask8 k, __m512d a, const int nidx);
|
|||
|
|
</pre>
|
|||
|
|
<pre>VEXTRACTF64x2 __m128d _mm512_maskz_extractf64x2_pd( __mmask8 k, __m512d a, const int nidx);
|
|||
|
|
</pre>
|
|||
|
|
<pre>VEXTRACTF64x2 __m128d _mm256_extractf64x2_pd(__m256d a, const int nidx);
|
|||
|
|
</pre>
|
|||
|
|
<pre>VEXTRACTF64x2 __m128d _mm256_mask_extractf64x2_pd(__m128d s, __mmask8 k, __m256d a, const int nidx);
|
|||
|
|
</pre>
|
|||
|
|
<pre>VEXTRACTF64x2 __m128d _mm256_maskz_extractf64x2_pd( __mmask8 k, __m256d a, const int nidx);
|
|||
|
|
</pre>
|
|||
|
|
<pre>VEXTRACTF64x4 __m256d _mm512_extractf64x4_pd( __m512d a, const int nidx);
|
|||
|
|
</pre>
|
|||
|
|
<pre>VEXTRACTF64x4 __m256d _mm512_mask_extractf64x4_pd(__m256d s, __mmask8 k, __m512d a, const int nidx);
|
|||
|
|
</pre>
|
|||
|
|
<pre>VEXTRACTF64x4 __m256d _mm512_maskz_extractf64x4_pd( __mmask8 k, __m512d a, const int nidx);
|
|||
|
|
</pre>
|
|||
|
|
<pre>VEXTRACTF128 __m128 _mm256_extractf128_ps (__m256 a, int offset);
|
|||
|
|
</pre>
|
|||
|
|
<pre>VEXTRACTF128 __m128d _mm256_extractf128_pd (__m256d a, int offset);
|
|||
|
|
</pre>
|
|||
|
|
<pre>VEXTRACTF128 __m128i_mm256_extractf128_si256(__m256i a, int offset);
|
|||
|
|
</pre>
|
|||
|
|
<h3 class="exceptions" id="simd-floating-point-exceptions">SIMD Floating-Point Exceptions<a class="anchor" href="#simd-floating-point-exceptions">
|
|||
|
|
¶
|
|||
|
|
</a></h3>
|
|||
|
|
<p>None.</p>
|
|||
|
|
<h3 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
|
|||
|
|
¶
|
|||
|
|
</a></h3>
|
|||
|
|
<p>VEX-encoded instructions, see <span class="not-imported">Table 2-23</span>, “Type 6 Class Exception Conditions.”</p>
|
|||
|
|
<p>EVEX-encoded instructions, see <span class="not-imported">Table 2-54</span>, “Type E6NF Class Exception Conditions.”</p>
|
|||
|
|
<p>Additionally:</p>
|
|||
|
|
<table>
|
|||
|
|
<tr>
|
|||
|
|
<td>#UD</td>
|
|||
|
|
<td>IF VEX.L = 0.</td></tr>
|
|||
|
|
<tr>
|
|||
|
|
<td>#UD</td>
|
|||
|
|
<td>If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.</td></tr></table><footer><p>
|
|||
|
|
This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
|
|||
|
|
inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
|
|||
|
|
ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
|
|||
|
|
</p></footer></body></html>
|