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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>PSHUFD
— Shuffle Packed Doublewords</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>PSHUFD
— Shuffle Packed Doublewords</h1>
<table>
<tr>
<th>Opcode/Instruction</th>
<th>Op/En</th>
<th>64/32 bit Mode Support</th>
<th>CPUID Feature Flag</th>
<th>Description</th></tr>
<tr>
<td>66 0F 70 /r ib PSHUFD xmm1, xmm2/m128, imm8</td>
<td>A</td>
<td>V/V</td>
<td>SSE2</td>
<td>Shuffle the doublewords in xmm2/m128 based on the encoding in imm8 and store the result in xmm1.</td></tr>
<tr>
<td>VEX.128.66.0F.WIG 70 /r ib VPSHUFD xmm1, xmm2/m128, imm8</td>
<td>A</td>
<td>V/V</td>
<td>AVX</td>
<td>Shuffle the doublewords in xmm2/m128 based on the encoding in imm8 and store the result in xmm1.</td></tr>
<tr>
<td>VEX.256.66.0F.WIG 70 /r ib VPSHUFD ymm1, ymm2/m256, imm8</td>
<td>A</td>
<td>V/V</td>
<td>AVX2</td>
<td>Shuffle the doublewords in ymm2/m256 based on the encoding in imm8 and store the result in ymm1.</td></tr>
<tr>
<td>EVEX.128.66.0F.W0 70 /r ib VPSHUFD xmm1 {k1}{z}, xmm2/m128/m32bcst, imm8</td>
<td>B</td>
<td>V/V</td>
<td>AVX512VL AVX512F</td>
<td>Shuffle the doublewords in xmm2/m128/m32bcst based on the encoding in imm8 and store the result in xmm1 using writemask k1.</td></tr>
<tr>
<td>EVEX.256.66.0F.W0 70 /r ib VPSHUFD ymm1 {k1}{z}, ymm2/m256/m32bcst, imm8</td>
<td>B</td>
<td>V/V</td>
<td>AVX512VL AVX512F</td>
<td>Shuffle the doublewords in ymm2/m256/m32bcst based on the encoding in imm8 and store the result in ymm1 using writemask k1.</td></tr>
<tr>
<td>EVEX.512.66.0F.W0 70 /r ib VPSHUFD zmm1 {k1}{z}, zmm2/m512/m32bcst, imm8</td>
<td>B</td>
<td>V/V</td>
<td>AVX512F</td>
<td>Shuffle the doublewords in zmm2/m512/m32bcst based on the encoding in imm8 and store the result in zmm1 using writemask k1.</td></tr></table>
<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
</a></h2>
<table>
<tr>
<th>Op/En</th>
<th>Tuple Type</th>
<th>Operand 1</th>
<th>Operand 2</th>
<th>Operand 3</th>
<th>Operand 4</th></tr>
<tr>
<td>A</td>
<td>N/A</td>
<td>ModRM:reg (w)</td>
<td>ModRM:r/m (r)</td>
<td>imm8</td>
<td>N/A</td></tr>
<tr>
<td>B</td>
<td>Full</td>
<td>ModRM:reg (w)</td>
<td>ModRM:r/m (r)</td>
<td>imm8</td>
<td>N/A</td></tr></table>
<h2 id="description">Description<a class="anchor" href="#description">
</a></h2>
<p>Copies doublewords from source operand (second operand) and inserts them in the destination operand (first operand) at the locations selected with the order operand (third operand). <span class="not-imported">Figure 4-16</span> shows the operation of the 256-bit VPSHUFD instruction and the encoding of the order operand. Each 2-bit field in the order operand selects the contents of one doubleword location within a 128-bit lane and copy to the target element in the destination operand. For example, bits 0 and 1 of the order operand targets the first doubleword element in the low and high 128-bit lane of the destination operand for 256-bit VPSHUFD. The encoded value of bits 1:0 of the order operand (see the field encoding in <span class="not-imported">Figure 4-16</span>) determines which doubleword element (from the respective 128-bit lane) of the source operand will be copied to doubleword 0 of the destination operand.</p>
<p>For 128-bit operation, only the low 128-bit lane are operative. The source operand can be an XMM register or a 128-bit memory location. The destination operand is an XMM register. The order operand is an 8-bit immediate. Note that this instruction permits a doubleword in the source operand to be copied to more than one doubleword location in the destination operand.</p>
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 8.917956000000004pt; fill: #000" textLength="118.73986719999999" x="196.38" y="13.386101000000053">X7 X6 X5 X4</text>
<text lengthAdjust="spacingAndGlyphs" style="font-size: 8.917956000000004pt; fill: #000" textLength="118.79900059999989" x="348.12" y="15.186101000000008">X3 X2 X1 X0</text>
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 8.917956000000004pt; fill: #000" textLength="31.137730600000026" x="219.1204879" y="93.36604950000003">00B - X4</text>
<text lengthAdjust="spacingAndGlyphs" style="font-size: 8.917956000000004pt; fill: #000" textLength="33.29769790000006" x="176.5803994" y="93.60737769999992">Encoding</text>
<text lengthAdjust="spacingAndGlyphs" style="font-size: 8.917956000000004pt; fill: #000" textLength="31.1481189000001" x="424.7392698" y="98.58589430000006">00B - X0</text>
<text lengthAdjust="spacingAndGlyphs" style="font-size: 8.917956000000004pt; fill: #000" textLength="33.348041200000125" x="382.19918129999996" y="98.76569180000001">Encoding</text>
<text lengthAdjust="spacingAndGlyphs" style="font-size: 8.917956000000004pt; fill: #000" textLength="31.137730600000026" x="219.1204879" y="102.3063803">01B - X5</text>
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 8.917956000000004pt; fill: #000" textLength="31.1481189000001" x="424.7392698" y="107.52542600000004">01B - X1</text>
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<p>10B - X2 ORDER 11B - X7 7 6 5 4 3 2 1 0 Operand 11B - X3 Operand</p>
<figcaption><span class="not-imported">Figure 4-16</span>. 256-bit VPSHUFD Instruction Operation</figcaption>
<p>The source operand can be an XMM register or a 128-bit memory location. The destination operand is an XMM register. The order operand is an 8-bit immediate. Note that this instruction permits a doubleword in the source operand to be copied to more than one doubleword location in the destination operand.</p>
<p>In 64-bit mode and not encoded in VEX/EVEX, using REX.R permits this instruction to access XMM8-XMM15.</p>
<p>128-bit Legacy SSE version: Bits (MAXVL-1:128) of the corresponding YMM destination register remain unchanged.</p>
<p>VEX.128 encoded version: The source operand can be an XMM register or a 128-bit memory location. The destination operand is an XMM register. Bits (MAXVL-1:128) of the corresponding ZMM register are zeroed.</p>
<p>VEX.256 encoded version: The source operand can be an YMM register or a 256-bit memory location. The destination operand is an YMM register. Bits (MAXVL-1:256) of the corresponding ZMM register are zeroed. Bits (255-1:128) of the destination stores the shuffled results of the upper 16 bytes of the source operand using the immediate byte as the order operand.</p>
<p>EVEX encoded version: The source operand can be an ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from a 32-bit memory location. The destination operand is a ZMM/YMM/XMM register updated according to the writemask.</p>
<p>Each 128-bit lane of the destination stores the shuffled results of the respective lane of the source operand using the immediate byte as the order operand.</p>
<p>Note: EVEX.vvvv and VEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.</p>
<h2 id="operation">Operation<a class="anchor" href="#operation">
</a></h2>
<h3 id="pshufd--128-bit-legacy-sse-version-">PSHUFD (128-bit Legacy SSE Version)<a class="anchor" href="#pshufd--128-bit-legacy-sse-version-">
</a></h3>
<pre>DEST[31:0] := (SRC &gt;&gt; (ORDER[1:0] * 32))[31:0];
DEST[63:32] := (SRC &gt;&gt; (ORDER[3:2] * 32))[31:0];
DEST[95:64] := (SRC &gt;&gt; (ORDER[5:4] * 32))[31:0];
DEST[127:96] := (SRC &gt;&gt; (ORDER[7:6] * 32))[31:0];
DEST[MAXVL-1:128] (Unmodified)
</pre>
<h3 id="vpshufd--vex-128-encoded-version-">VPSHUFD (VEX.128 Encoded Version)<a class="anchor" href="#vpshufd--vex-128-encoded-version-">
</a></h3>
<pre>DEST[31:0] := (SRC &gt;&gt; (ORDER[1:0] * 32))[31:0];
DEST[63:32] := (SRC &gt;&gt; (ORDER[3:2] * 32))[31:0];
DEST[95:64] := (SRC &gt;&gt; (ORDER[5:4] * 32))[31:0];
DEST[127:96] := (SRC &gt;&gt; (ORDER[7:6] * 32))[31:0];
DEST[MAXVL-1:128] := 0
</pre>
<h3 id="vpshufd--vex-256-encoded-version-">VPSHUFD (VEX.256 Encoded Version)<a class="anchor" href="#vpshufd--vex-256-encoded-version-">
</a></h3>
<pre>DEST[31:0] := (SRC[127:0] &gt;&gt; (ORDER[1:0] * 32))[31:0];
DEST[63:32] := (SRC[127:0] &gt;&gt; (ORDER[3:2] * 32))[31:0];
DEST[95:64] := (SRC[127:0] &gt;&gt; (ORDER[5:4] * 32))[31:0];
DEST[127:96] := (SRC[127:0] &gt;&gt; (ORDER[7:6] * 32))[31:0];
DEST[159:128] := (SRC[255:128] &gt;&gt; (ORDER[1:0] * 32))[31:0];
DEST[191:160] := (SRC[255:128] &gt;&gt; (ORDER[3:2] * 32))[31:0];
DEST[223:192] := (SRC[255:128] &gt;&gt; (ORDER[5:4] * 32))[31:0];
DEST[255:224] := (SRC[255:128] &gt;&gt; (ORDER[7:6] * 32))[31:0];
DEST[MAXVL-1:256] := 0
</pre>
<h3 id="vpshufd--evex-encoded-versions-">VPSHUFD (EVEX Encoded Versions)<a class="anchor" href="#vpshufd--evex-encoded-versions-">
</a></h3>
<pre>(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1
i := j * 32
IF (EVEX.b = 1) AND (SRC *is memory*)
THEN TMP_SRC[i+31:i] := SRC[31:0]
ELSE TMP_SRC[i+31:i] := SRC[i+31:i]
FI;
ENDFOR;
IF VL &gt;= 128
TMP_DEST[31:0] := (TMP_SRC[127:0] &gt;&gt; (ORDER[1:0] * 32))[31:0];
TMP_DEST[63:32] := (TMP_SRC[127:0] &gt;&gt; (ORDER[3:2] * 32))[31:0];
TMP_DEST[95:64] := (TMP_SRC[127:0] &gt;&gt; (ORDER[5:4] * 32))[31:0];
TMP_DEST[127:96] := (TMP_SRC[127:0] &gt;&gt; (ORDER[7:6] * 32))[31:0];
FI;
IF VL &gt;= 256
TMP_DEST[159:128] := (TMP_SRC[255:128]
&gt;&gt; (ORDER[1:0] * 32))[31:0];
TMP_DEST[191:160] := (TMP_SRC[255:128]
&gt;&gt; (ORDER[3:2] * 32))[31:0];
TMP_DEST[223:192] := (TMP_SRC[255:128]
&gt;&gt; (ORDER[5:4] * 32))[31:0];
TMP_DEST[255:224] := (TMP_SRC[255:128]
&gt;&gt; (ORDER[7:6] * 32))[31:0];
FI;
IF VL &gt;= 512
TMP_DEST[287:256] := (TMP_SRC[383:256]
&gt;&gt; (ORDER[1:0] * 32))[31:0];
TMP_DEST[319:288] := (TMP_SRC[383:256]
&gt;&gt; (ORDER[3:2] * 32))[31:0];
TMP_DEST[351:320] := (TMP_SRC[383:256]
&gt;&gt; (ORDER[5:4] * 32))[31:0];
TMP_DEST[383:352] := (TMP_SRC[383:256]
&gt;&gt; (ORDER[7:6] * 32))[31:0];
TMP_DEST[415:384] := (TMP_SRC[511:384]
&gt;&gt; (ORDER[1:0] * 32))[31:0];
TMP_DEST[447:416] := (TMP_SRC[511:384]
&gt;&gt; (ORDER[3:2] * 32))[31:0];
TMP_DEST[479:448] := (TMP_SRC[511:384]
&gt;&gt; (ORDER[5:4] * 32))[31:0];
TMP_DEST[511:480] := (TMP_SRC[511:384]
&gt;&gt; (ORDER[7:6] * 32))[31:0];
FI;
FOR j := 0 TO KL-1
i := j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] := TMP_DEST[i+31:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+31:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
</pre>
<h2 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
</a></h2>
<pre>VPSHUFD __m512i _mm512_shuffle_epi32(__m512i a, int n );
</pre>
<pre>VPSHUFD __m512i _mm512_mask_shuffle_epi32(__m512i s, __mmask16 k, __m512i a, int n );
</pre>
<pre>VPSHUFD __m512i _mm512_maskz_shuffle_epi32( __mmask16 k, __m512i a, int n );
</pre>
<pre>VPSHUFD __m256i _mm256_mask_shuffle_epi32(__m256i s, __mmask8 k, __m256i a, int n );
</pre>
<pre>VPSHUFD __m256i _mm256_maskz_shuffle_epi32( __mmask8 k, __m256i a, int n );
</pre>
<pre>VPSHUFD __m128i _mm_mask_shuffle_epi32(__m128i s, __mmask8 k, __m128i a, int n );
</pre>
<pre>VPSHUFD __m128i _mm_maskz_shuffle_epi32( __mmask8 k, __m128i a, int n );
</pre>
<pre>(V)PSHUFD __m128i _mm_shuffle_epi32(__m128i a, int n)
</pre>
<pre>VPSHUFD __m256i _mm256_shuffle_epi32(__m256i a, const int n)
</pre>
<h2 id="flags-affected">Flags Affected<a class="anchor" href="#flags-affected">
</a></h2>
<p>None.</p>
<h2 class="exceptions" id="simd-floating-point-exceptions">SIMD Floating-Point Exceptions<a class="anchor" href="#simd-floating-point-exceptions">
</a></h2>
<p>None.</p>
<h2 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
</a></h2>
<p>Non-EVEX-encoded instruction, see <span class="not-imported">Table 2-21</span>, “Type 4 Class Exception Conditions.”</p>
<p>EVEX-encoded instruction, see <span class="not-imported">Table 2-50</span>, “Type E4NF Class Exception Conditions.”</p>
<p>Additionally:</p>
<table>
<tr>
<td>#UD</td>
<td>If VEX.vvvv ≠ 1111B or EVEX.vvvv ≠ 1111B.</td></tr></table><footer><p>
This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
</p></footer></body></html>
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