forked from NRZCode/ia32-64
109 lines
5.5 KiB
HTML
109 lines
5.5 KiB
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>PCMPISTRM
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— Packed Compare Implicit Length Strings, Return Mask</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>PCMPISTRM
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— Packed Compare Implicit Length Strings, Return Mask</h1>
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<table>
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<tr>
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<th>Opcode/Instruction</th>
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<th>Op/En</th>
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<th>64/32 bit Mode Support</th>
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<th>CPUID Feature Flag</th>
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<th>Description</th></tr>
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<tr>
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<td>66 0F 3A 62 /r imm8 PCMPISTRM xmm1, xmm2/m128, imm8</td>
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<td>RM</td>
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<td>V/V</td>
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<td>SSE4_2</td>
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<td>Perform a packed comparison of string data with implicit lengths, generating a mask, and storing the result in XMM0.</td></tr>
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<tr>
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<td>VEX.128.66.0F3A.WIG 62 /r ib VPCMPISTRM xmm1, xmm2/m128, imm8</td>
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<td>RM</td>
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<td>V/V</td>
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<td>AVX</td>
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<td>Perform a packed comparison of string data with implicit lengths, generating a Mask, and storing the result in XMM0.</td></tr></table>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Operand 3</th>
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<th>Operand 4</th></tr>
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<tr>
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<td>RM</td>
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<td>ModRM:reg (r)</td>
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<td>ModRM:r/m (r)</td>
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<td>imm8</td>
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<td>N/A</td></tr></table>
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<h2 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h2>
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<p>The instruction compares data from two strings based on the encoded value in the imm8 byte (see Section 4.1, “Imm8 Control Byte Operation for PCMPESTRI / PCMPESTRM / PCMPISTRI / PCMPISTRM”) generating a mask stored to XMM0.</p>
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<p>Each string is represented by a single value. The value is an xmm (or possibly m128 for the second operand) which contains the data elements of the string (byte or word data). Each input byte/word is augmented with a valid/invalid tag. A byte/word is considered valid only if it has a lower index than the least significant null byte/word. (The least significant null byte/word is also considered invalid.)</p>
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<p>The comparison and aggregation operation are performed according to the encoded value of imm8 bit fields (see Section 4.1). As defined by imm8[6], IntRes2 is then either stored to the least significant bits of XMM0 (zero extended to 128 bits) or expanded into a byte/word-mask and then stored to XMM0.</p>
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<p>Note that the Arithmetic Flags are written in a non-standard manner in order to supply the most relevant information:</p>
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<p>CFlag – Reset if IntRes2 is equal to zero, set otherwise</p>
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<p>ZFlag – Set if any byte/word of xmm2/mem128 is null, reset otherwise</p>
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<p>SFlag – Set if any byte/word of xmm1 is null, reset otherwise</p>
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<p>OFlag – IntRes2[0]</p>
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<p>AFlag – Reset</p>
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<p>PFlag – Reset</p>
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<p>Note: In VEX.128 encoded versions, bits (MAXVL-1:128) of XMM0 are zeroed. VEX.vvvv is reserved and must be 1111b, VEX.L must be 0, otherwise the instruction will #UD.</p>
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<h2 id="effective-operand-size">Effective Operand Size<a class="anchor" href="#effective-operand-size">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Operating mode/size</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Result</th></tr>
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<tr>
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<td>16 bit</td>
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<td>xmm</td>
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<td>xmm/m128</td>
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<td>XMM0</td></tr>
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<tr>
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<td>32 bit</td>
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<td>xmm</td>
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<td>xmm/m128</td>
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<td>XMM0</td></tr>
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<tr>
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<td>64 bit</td>
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<td>xmm</td>
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<td>xmm/m128</td>
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<td>XMM0</td></tr></table>
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<h2 id="intel-c-c++-compiler-intrinsic-equivalent-for-returning-mask">Intel C/C++ Compiler Intrinsic Equivalent For Returning Mask<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent-for-returning-mask">
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¶
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</a></h2>
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<p>__m128i _mm_cmpistrm (__m128i a, __m128i b, const int mode);</p>
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<h2 id="intel-c-c++-compiler-intrinsics-for-reading-eflag-results">Intel C/C++ Compiler Intrinsics For Reading EFlag Results<a class="anchor" href="#intel-c-c++-compiler-intrinsics-for-reading-eflag-results">
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¶
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</a></h2>
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<p>int _mm_cmpistra (__m128i a, __m128i b, const int mode);</p>
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<p>int _mm_cmpistrc (__m128i a, __m128i b, const int mode);</p>
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<p>int _mm_cmpistro (__m128i a, __m128i b, const int mode);</p>
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<p>int _mm_cmpistrs (__m128i a, __m128i b, const int mode);</p>
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<p>int _mm_cmpistrz (__m128i a, __m128i b, const int mode);</p>
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<h2 class="exceptions" id="simd-floating-point-exceptions">SIMD Floating-Point Exceptions<a class="anchor" href="#simd-floating-point-exceptions">
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¶
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</a></h2>
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<p>None.</p>
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<h2 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
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¶
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</a></h2>
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<p>See <span class="not-imported">Table 2-21</span>, “Type 4 Class Exception Conditions,” additionally, this instruction does not cause #GP if the memory operand is not aligned to 16 Byte boundary, and:</p>
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<table>
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<tr>
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<td rowspan="2">#UD</td>
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<td>If VEX.L = 1.</td></tr>
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<tr>
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<td>If VEX.vvvv ≠ 1111B.</td></tr></table><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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