forked from NRZCode/ia32-64
824 lines
116 KiB
HTML
824 lines
116 KiB
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>MPSADBW
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— Compute Multiple Packed Sums of Absolute Difference</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>MPSADBW
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— Compute Multiple Packed Sums of Absolute Difference</h1>
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<table>
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<tr>
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<th>Opcode/Instruction</th>
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<th>Op/En</th>
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<th>64/32-bit Mode</th>
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<th>CPUID Feature Flag</th>
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<th>Description</th></tr>
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<tr>
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<td>66 0F 3A 42 /r ib MPSADBW xmm1, xmm2/m128, imm8</td>
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<td>RMI</td>
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<td>V/V</td>
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<td>SSE4_1</td>
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<td>Sums absolute 8-bit integer difference of adjacent groups of 4 byte integers in xmm1 and xmm2/m128 and writes the results in xmm1. Starting offsets within xmm1 and xmm2/m128 are determined by imm8.</td></tr>
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<tr>
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<td>VEX.128.66.0F3A.WIG 42 /r ib VMPSADBW xmm1, xmm2, xmm3/m128, imm8</td>
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<td>RVMI</td>
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<td>V/V</td>
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<td>AVX</td>
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<td>Sums absolute 8-bit integer difference of adjacent groups of 4 byte integers in xmm2 and xmm3/m128 and writes the results in xmm1. Starting offsets within xmm2 and xmm3/m128 are determined by imm8.</td></tr>
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<tr>
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<td>VEX.256.66.0F3A.WIG 42 /r ib VMPSADBW ymm1, ymm2, ymm3/m256, imm8</td>
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<td>RVMI</td>
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<td>V/V</td>
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<td>AVX2</td>
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<td>Sums absolute 8-bit integer difference of adjacent groups of 4 byte integers in xmm2 and ymm3/m128 and writes the results in ymm1. Starting offsets within ymm2 and xmm3/m128 are determined by imm8.</td></tr></table>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Operand 3</th>
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<th>Operand 4</th></tr>
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<tr>
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<td>RMI</td>
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<td>ModRM:reg (r, w)</td>
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<td>ModRM:r/m (r)</td>
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<td>imm8</td>
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<td>N/A</td></tr>
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<tr>
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<td>RVMI</td>
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<td>ModRM:reg (w)</td>
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<td>VEX.vvvv (r)</td>
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<td>ModRM:r/m (r)</td>
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<td>imm8</td></tr></table>
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<h2 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h2>
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<p>(V)MPSADBW calculates packed word results of sum-absolute-difference (SAD) of unsigned bytes from two blocks of 32-bit dword elements, using two select fields in the immediate byte to select the offsets of the two blocks within the first source operand and the second operand. Packed SAD word results are calculated within each 128-bit lane. Each SAD word result is calculated between a stationary block_2 (whose offset within the second source operand is selected by a two bit select control, multiplied by 32 bits) and a sliding block_1 at consecutive byte-granular position within the first source operand. The offset of the first 32-bit block of block_1 is selectable using a one bit select control, multiplied by 32 bits.</p>
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<p>128-bit Legacy SSE version: Imm8[1:0]*32 specifies the bit offset of block_2 within the second source operand. Imm[2]*32 specifies the initial bit offset of the block_1 within the first source operand. The first source operand and destination operand are the same. The first source and destination operands are XMM registers. The second source operand is either an XMM register or a 128-bit memory location. Bits (MAXVL-1:128) of the corresponding YMM destination register remain unchanged. Bits 7:3 of the immediate byte are ignored.</p>
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<p>VEX.128 encoded version: Imm8[1:0]*32 specifies the bit offset of block_2 within the second source operand. Imm[2]*32 specifies the initial bit offset of the block_1 within the first source operand. The first source and destination operands are XMM registers. The second source operand is either an XMM register or a 128-bit memory location. Bits (127:128) of the corresponding YMM register are zeroed. Bits 7:3 of the immediate byte are ignored.</p>
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<p>VEX.256 encoded version: The sum-absolute-difference (SAD) operation is repeated 8 times for MPSADW between the same block_2 (fixed offset within the second source operand) and a variable block_1 (offset is shifted by 8 bits for each SAD operation) in the first source operand. Each 16-bit result of eight SAD operations between block_2 and block_1 is written to the respective word in the lower 128 bits of the destination operand.</p>
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<p>Additionally, VMPSADBW performs another eight SAD operations on block_4 of the second source operand and block_3 of the first source operand. (Imm8[4:3]*32 + 128) specifies the bit offset of block_4 within the second source operand. (Imm[5]*32+128) specifies the initial bit offset of the block_3 within the first source operand. Each 16-bit result of eight SAD operations between block_4 and block_3 is written to the respective word in the upper 128 bits of the destination operand.</p>
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<p>The first source operand is a YMM register. The second source register can be a YMM register or a 256-bit memory location. The destination operand is a YMM register. Bits 7:6 of the immediate byte are ignored.</p>
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<p>Note: If VMPSADBW is encoded with VEX.L= 1, an attempt to execute the instruction encoded with VEX.L= 1 will cause an #UD exception.</p>
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<figure id="fig-4-5">
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<path d="M 300.66 326.70004 L 300.3 326.34004 L 279.48 346.32004 L 279.84000000000003 346.68004" style="fill: rgb(0%, 0%, 0%); fill-rule: nonzero"></path>
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<path d="M 250.86 349.26004 L 250.62 348.90004 L 249.66000000000003 349.50004 L 249.9 349.86004" style="fill: rgb(0%, 0%, 0%); fill-rule: nonzero"></path>
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<path d="M 250.08 349.26004 L 251.58 350.46004 L 252.42000000000002 351.12004 L 251.4 351.36004 L 243.42000000000002 353.64004 L 244.56 352.38004 L 248.94000000000003 347.52004 L 249.66000000000003 346.74004 L 249.84 347.70004 L 249.72 348.18004 L 245.34 353.04004 L 244.56 352.38004 L 244.8 352.20004 L 251.10000000000002 350.40004 L 251.4 351.36004 L 250.98000000000002 351.30004 L 249.48000000000002 350.10004" style="fill: rgb(0%, 0%, 0%); fill-rule: nonzero"></path>
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<path d="M 249.84 347.70004 L 250.26 349.56004 L 249.48 350.10004 L 249.3 349.98004 L 249.3 349.80004 L 248.88 347.94004" style="fill: rgb(0%, 0%, 0%); fill-rule: nonzero"></path>
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<path d="M 249.78 349.68004 L 251.28 350.88004 L 244.98 352.68004 L 249.36 347.82004" style="fill: rgb(0%, 0%, 0%); fill-rule: evenodd"></path>
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<path d="M 280.98 330.60004 L 281.16 330.48004 L 280.92 330.06003999999996 L 280.74 330.18003999999996" style="fill: rgb(0%, 0%, 0%); fill-rule: nonzero"></path>
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|
<path d="M 250.86 349.32004 L 250.68 349.44004 L 250.44000000000003 349.02004 L 250.62 348.90004" style="fill: rgb(0%, 0%, 0%); fill-rule: nonzero"></path>
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|||
|
|
<path d="M 280.98 330.60004 L 280.74 330.18003999999996 L 250.62 348.90004 L 250.86 349.32003999999995" style="fill: rgb(0%, 0%, 0%); fill-rule: nonzero"></path>
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|||
|
|
<path d="M 213.18 351.54004 L 213.06 351.06003999999996 L 211.98000000000002 351.42004 L 212.1 351.90004" style="fill: rgb(0%, 0%, 0%); fill-rule: nonzero"></path>
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|||
|
|
<path d="M 212.4 351.30004 L 213.66 352.80004 L 214.38 353.58004 L 213.3 353.70004 L 206.70000000000002 354.18004 L 204.96 354.30004 L 206.34 353.28004000000004 L 211.68 349.38004 L 212.58 348.72004000000004 L 212.58 349.74004 L 212.34 350.16004000000004 L 207.0 354.06004 L 206.34 353.28004000000004 L 206.64000000000001 353.16004000000004 L 213.24 352.68004 L 213.3 353.70004 L 212.94 353.52004000000005 L 211.68 352.02004000000005" style="fill: rgb(0%, 0%, 0%); fill-rule: nonzero"></path>
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<path d="M 212.58 349.74004 L 212.58 351.66004000000004 L 211.68 352.02004 L 211.56 351.84004000000004 L 211.5 351.66004000000004 L 211.5 349.74004" style="fill: rgb(0%, 0%, 0%); fill-rule: nonzero"></path>
|
|||
|
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<path d="M 212.04 351.66004 L 213.29999999999998 353.16004 L 206.7 353.64004 L 212.04 349.74003999999996" style="fill: rgb(0%, 0%, 0%); fill-rule: evenodd"></path>
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|||
|
|
<path d="M 256.62 335.58004 L 256.86 335.52004 L 256.68 335.04004 L 256.44 335.10004" style="fill: rgb(0%, 0%, 0%); fill-rule: nonzero"></path>
|
|||
|
|
<path d="M 213.24 351.54004 L 213.0 351.60004 L 212.82000000000002 351.12003999999996 L 213.06 351.06003999999996" style="fill: rgb(0%, 0%, 0%); fill-rule: nonzero"></path>
|
|||
|
|
<path d="M 256.62 335.58004 L 256.44 335.10004 L 213.06 351.06004 L 213.24 351.54004" style="fill: rgb(0%, 0%, 0%); fill-rule: nonzero"></path>
|
|||
|
|
<path d="M 289.2 297.24004 L 288.84 296.88004 L 287.94 297.66004000000004 L 288.3 298.02004" style="fill: rgb(0%, 0%, 0%); fill-rule: nonzero"></path>
|
|||
|
|
<path d="M 288.36 297.42004 L 290.04 298.38003999999995 L 290.94 298.86003999999997 L 289.98 299.28004 L 283.98 301.98004 L 282.36 302.70003999999994 L 283.38 301.26003999999995 L 287.04 295.74003999999996 L 287.58000000000004 294.84004 L 287.94 295.80003999999997 L 287.88 296.28004 L 284.22 301.80003999999997 L 283.38 301.26003999999995 L 283.56 301.08004 L 289.56 298.38003999999995 L 289.98 299.28004 L 289.56 299.22004 L 287.88 298.26003999999995" style="fill: rgb(0%, 0%, 0%); fill-rule: nonzero"></path>
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|||
|
|
<path d="M 287.94 295.80004 L 288.6 297.66004000000004 L 287.88 298.26004 L 287.7 298.20004 L 287.64 298.02004000000005 L 286.98 296.16004000000004" style="fill: rgb(0%, 0%, 0%); fill-rule: nonzero"></path>
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|||
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|
<path d="M 288.12 297.84004 L 289.8 298.80003999999997 L 283.8 301.50004 L 287.46 295.98004" style="fill: rgb(0%, 0%, 0%); fill-rule: evenodd"></path>
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|||
|
|
<path d="M 337.8 256.02004 L 337.98 255.90004 L 337.68 255.54003999999998 L 337.5 255.66003999999998" style="fill: rgb(0%, 0%, 0%); fill-rule: nonzero"></path>
|
|||
|
|
<path d="M 289.2 297.24004 L 289.02 297.36004 L 288.71999999999997 297.00004 L 288.9 296.88004" style="fill: rgb(0%, 0%, 0%); fill-rule: nonzero"></path>
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|||
|
|
<path d="M 337.8 256.02004 L 337.5 255.66003999999998 L 288.9 296.88004 L 289.2 297.24004" style="fill: rgb(0%, 0%, 0%); fill-rule: nonzero"></path>
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|||
|
|
<path d="M 266.46 302.94004 L 266.21999999999997 302.58004 L 265.26 303.24004 L 265.5 303.60004000000004" style="fill: rgb(0%, 0%, 0%); fill-rule: nonzero"></path>
|
|||
|
|
<path d="M 265.68 303.00004 L 267.24 304.08004 L 268.08 304.68004 L 267.06 304.98004000000003 L 260.82 307.08004 L 259.2 307.68004 L 260.28000000000003 306.30004 L 264.48 301.20004 L 265.14 300.36004 L 265.38 301.38004 L 265.26 301.80004 L 261.06 306.90004 L 260.28000000000003 306.30004 L 260.52 306.12004 L 266.76 304.02004 L 267.06 304.98004000000003 L 266.64 304.92004000000003 L 265.08 303.84004" style="fill: rgb(0%, 0%, 0%); fill-rule: nonzero"></path>
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|||
|
|
<path d="M 265.38 301.38004 L 265.86 303.30004 L 265.08 303.84004 L 264.96 303.72004 L 264.9 303.54004000000003 L 264.42 301.62004" style="fill: rgb(0%, 0%, 0%); fill-rule: nonzero"></path>
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|
<path d="M 265.38 303.42004 L 266.94 304.50003999999996 L 260.7 306.60004 L 264.9 301.50003999999996" style="fill: rgb(0%, 0%, 0%); fill-rule: evenodd"></path>
|
|||
|
|
<path d="M 334.20000000000005 256.08004 L 334.38000000000005 255.96004 L 334.08000000000004 255.54003999999998 L 333.90000000000003 255.66003999999998" style="fill: rgb(0%, 0%, 0%); fill-rule: nonzero"></path>
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|
<path d="M 266.52 303.00004 L 266.34 303.12004 L 266.03999999999996 302.70004 L 266.21999999999997 302.58004" style="fill: rgb(0%, 0%, 0%); fill-rule: nonzero"></path>
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|||
|
|
<path d="M 334.20000000000005 256.08004 L 333.90000000000003 255.66003999999998 L 266.22 302.58004 L 266.52000000000004 303.00004" style="fill: rgb(0%, 0%, 0%); fill-rule: nonzero"></path>
|
|||
|
|
<path d="M 244.20000000000002 306.66004 L 243.96 306.30003999999997 L 242.94000000000003 306.90004 L 243.18 307.26004" style="fill: rgb(0%, 0%, 0%); fill-rule: nonzero"></path>
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|||
|
|
<path d="M 243.36 306.66004 L 244.86 307.86003999999997 L 245.76000000000002 308.52004 L 244.62 308.76004 L 238.26000000000002 310.44003999999995 L 236.64000000000001 310.86003999999997 L 237.78 309.66004 L 242.28 304.86003999999997 L 243.0 304.08004 L 243.18 305.10004 L 243.06 305.52004 L 238.56 310.32004 L 237.78 309.66004 L 238.08 309.48004 L 244.44000000000003 307.80003999999997 L 244.62 308.76004 L 244.26000000000002 308.70004 L 242.76000000000002 307.50003999999996" style="fill: rgb(0%, 0%, 0%); fill-rule: nonzero"></path>
|
|||
|
|
<path d="M 243.18 305.10004 L 243.54000000000002 307.02004 L 242.76000000000002 307.50003999999996 L 242.58 307.38003999999995 L 242.58 307.14004 L 242.22 305.22004" style="fill: rgb(0%, 0%, 0%); fill-rule: nonzero"></path>
|
|||
|
|
<path d="M 243.06 307.08004 L 244.56 308.28004 L 238.2 309.96004 L 242.7 305.16004" style="fill: rgb(0%, 0%, 0%); fill-rule: evenodd"></path>
|
|||
|
|
<path d="M 331.14 255.48003999999997 L 331.32 255.36003999999997 L 331.08 254.94003999999995 L 330.9 255.06003999999996" style="fill: rgb(0%, 0%, 0%); fill-rule: nonzero"></path>
|
|||
|
|
<path d="M 244.20000000000002 306.72004 L 244.02 306.84004 L 243.78000000000003 306.42004 L 243.96 306.30003999999997" style="fill: rgb(0%, 0%, 0%); fill-rule: nonzero"></path>
|
|||
|
|
<path d="M 331.14 255.48003999999997 L 330.9 255.06003999999996 L 243.95999999999998 306.30003999999997 L 244.2 306.72004" style="fill: rgb(0%, 0%, 0%); fill-rule: nonzero"></path>
|
|||
|
|
<path d="M 220.56 310.26004 L 220.32 309.78004 L 219.3 310.32004 L 219.54 310.80004" style="fill: rgb(0%, 0%, 0%); fill-rule: nonzero"></path>
|
|||
|
|
<path d="M 219.78 310.20004 L 221.22 311.46004 L 222.0 312.06004 L 220.92 312.30004 L 214.5 313.68004 L 212.82 314.10004 L 214.08 312.84004 L 218.82 308.28004 L 219.54 307.56004 L 219.66 308.58004 L 219.54 309.00004 L 214.8 313.56004 L 214.08 312.84004 L 214.32 312.72004 L 220.74 311.34004 L 220.92 312.30004 L 220.5 312.18004 L 219.06 310.92004000000003" style="fill: rgb(0%, 0%, 0%); fill-rule: nonzero"></path>
|
|||
|
|
<path d="M 219.66 308.58004 L 219.9 310.50004 L 219.06 310.92004 L 218.94 310.80004 L 218.94 310.62004 L 218.7 308.70004" style="fill: rgb(0%, 0%, 0%); fill-rule: nonzero"></path>
|
|||
|
|
<path d="M 219.42000000000002 310.56003999999996 L 220.86 311.82003999999995 L 214.44000000000003 313.20003999999994 L 219.18 308.64003999999994" style="fill: rgb(0%, 0%, 0%); fill-rule: evenodd"></path>
|
|||
|
|
<path d="M 323.34000000000003 255.48003999999997 L 323.52000000000004 255.36003999999997 L 323.28000000000003 254.94003999999995 L 323.1 255.06003999999996" style="fill: rgb(0%, 0%, 0%); fill-rule: nonzero"></path>
|
|||
|
|
<path d="M 220.56 310.26004 L 220.38 310.38004 L 220.14000000000001 309.96004 L 220.32 309.84004" style="fill: rgb(0%, 0%, 0%); fill-rule: nonzero"></path>
|
|||
|
|
<path d="M 323.34000000000003 255.48003999999997 L 323.1 255.06003999999996 L 220.32000000000005 309.84004 L 220.56000000000003 310.26004" style="fill: rgb(0%, 0%, 0%); fill-rule: nonzero"></path>
|
|||
|
|
<rect height="0.23999" style="fill: rgb(0%, 0%, 0%)" width="0.47998" x="379.98" y="226.80005"></rect>
|
|||
|
|
<rect height="3.84" style="fill: rgb(0%, 0%, 0%)" width="0.47998" x="379.98" y="227.04004000000003"></rect>
|
|||
|
|
<rect height="0.24002" style="fill: rgb(0%, 0%, 0%)" width="0.48001000000000005" x="412.38" y="276.60002"></rect>
|
|||
|
|
<rect height="4.44" style="fill: rgb(0%, 0%, 0%)" width="0.48001000000000005" x="412.38" y="276.84004"></rect>
|
|||
|
|
<text lengthAdjust="spacingAndGlyphs" style="font-size: 8.917956000000004pt; fill: #000" textLength="61.075212999999906" x="366.24" y="25.68614100000002">Imm[4:3]*32+128</text>
|
|||
|
|
<text lengthAdjust="spacingAndGlyphs" style="font-size: 8.917956000000004pt; fill: #000" textLength="13.320997000000034" x="442.62016980000004" y="34.32717309999998">128</text>
|
|||
|
|
<text lengthAdjust="spacingAndGlyphs" style="font-size: 8.917956000000004pt; fill: #000" textLength="13.320996999999977" x="156.60150320000002" y="35.10709469999995">255</text>
|
|||
|
|
<text lengthAdjust="spacingAndGlyphs" style="font-size: 8.917956000000004pt; fill: #000" textLength="13.320996999999977" x="219.18142150000003" y="35.2868921999999">224</text>
|
|||
|
|
<text lengthAdjust="spacingAndGlyphs" style="font-size: 8.917956000000004pt; fill: #000" textLength="13.320997000000034" x="292.6211088" y="35.526622199999906">192</text>
|
|||
|
|
<text lengthAdjust="spacingAndGlyphs" style="font-size: 8.917956000000004pt; fill: #000" textLength="16.44387979999999" x="160.32072010000002" y="68.70568949999995">Src2</text>
|
|||
|
|
<text lengthAdjust="spacingAndGlyphs" style="font-size: 8.917956000000004pt; fill: #000" textLength="32.27724720000009" x="349.74" y="72.48614099999998">Abs. Diff.</text>
|
|||
|
|
<text lengthAdjust="spacingAndGlyphs" style="font-size: 8.917956000000004pt; fill: #000" textLength="54.42030819999985" x="401.21980340000005" y="75.72578299999998">Imm[5]*32+128</text>
|
|||
|
|
<text lengthAdjust="spacingAndGlyphs" style="font-size: 8.917956000000004pt; fill: #000" textLength="16.45826359999998" x="158.76087690000003" y="125.88528999999994">Src1</text>
|
|||
|
|
<text lengthAdjust="spacingAndGlyphs" style="font-size: 8.917956000000004pt; fill: #000" textLength="16.435888799999987" x="387.0" y="132.90614100000005">Sum</text>
|
|||
|
|
<text lengthAdjust="spacingAndGlyphs" style="font-size: 9.097753499999953pt; fill: #000" textLength="51.960678400000006" x="402.0003186" y="155.286141">144 128</text>
|
|||
|
|
<text lengthAdjust="spacingAndGlyphs" style="font-size: 8.917956000000004pt; fill: #000" textLength="13.320996999999977" x="174.42143319999997" y="156.1259951">255</text>
|
|||
|
|
<text lengthAdjust="spacingAndGlyphs" style="font-size: 8.917956000000004pt; fill: #000" textLength="40.015731599999924" x="154.3215556" y="186.3072741000001">Destination</text>
|
|||
|
|
<text lengthAdjust="spacingAndGlyphs" style="font-size: 8.917956000000004pt; fill: #000" textLength="43.08747199999988" x="371.82" y="223.92614100000003">Imm[1:0]*32</text>
|
|||
|
|
<text lengthAdjust="spacingAndGlyphs" style="font-size: 8.917956pt; fill: #000" textLength="4.442995999999994" x="448.2001698" y="232.50724060000005">0</text>
|
|||
|
|
<text lengthAdjust="spacingAndGlyphs" style="font-size: 8.917956000000004pt; fill: #000" textLength="13.320996999999977" x="162.1815032" y="233.28716220000007">127</text>
|
|||
|
|
<text lengthAdjust="spacingAndGlyphs" style="font-size: 8.917956000000004pt; fill: #000" textLength="8.881996499999985" x="224.821354" y="233.52689220000008">96</text>
|
|||
|
|
<text lengthAdjust="spacingAndGlyphs" style="font-size: 8.917956000000004pt; fill: #000" textLength="8.881996500000014" x="298.20110880000004" y="233.70668970000008">64</text>
|
|||
|
|
<text lengthAdjust="spacingAndGlyphs" style="font-size: 8.917956000000004pt; fill: #000" textLength="16.45826359999998" x="165.96065259999995" y="266.9456895">Src2</text>
|
|||
|
|
<text lengthAdjust="spacingAndGlyphs" style="font-size: 8.917956000000004pt; fill: #000" textLength="32.27804630000003" x="355.32" y="270.666141">Abs. Diff.</text>
|
|||
|
|
<text lengthAdjust="spacingAndGlyphs" style="font-size: 8.917956000000004pt; fill: #000" textLength="36.48370959999983" x="406.7998034" y="273.90585050000004">Imm[2]*32</text>
|
|||
|
|
<text lengthAdjust="spacingAndGlyphs" style="font-size: 8.917956000000004pt; fill: #000" textLength="16.45826359999998" x="169.1416642" y="321.12663150000014">Src1</text>
|
|||
|
|
<text lengthAdjust="spacingAndGlyphs" style="font-size: 8.917956000000004pt; fill: #000" textLength="16.435888799999987" x="392.64" y="331.146141">Sum</text>
|
|||
|
|
<text lengthAdjust="spacingAndGlyphs" style="font-size: 9.097753499999953pt; fill: #000" textLength="43.02274490000002" x="407.6402511" y="353.526141">16 0</text>
|
|||
|
|
<text lengthAdjust="spacingAndGlyphs" style="font-size: 8.917956000000004pt; fill: #000" textLength="13.320996999999977" x="180.0014332" y="354.3060626">127</text>
|
|||
|
|
<text lengthAdjust="spacingAndGlyphs" style="font-size: 8.917956000000004pt; fill: #000" textLength="40.0173298" x="157.14098589999995" y="386.52541080000003">Destination</text></g></svg>
|
|||
|
|
<figcaption><a href='mpsadbw.html#fig-4-5'>Figure 4-5</a>. 256-bit VMPSADBW Operation</figcaption></figure>
|
|||
|
|
<h2 id="operation">Operation<a class="anchor" href="#operation">
|
|||
|
|
¶
|
|||
|
|
</a></h2>
|
|||
|
|
<h3 id="vmpsadbw--vex-256-encoded-version-">VMPSADBW (VEX.256 Encoded Version)<a class="anchor" href="#vmpsadbw--vex-256-encoded-version-">
|
|||
|
|
¶
|
|||
|
|
</a></h3>
|
|||
|
|
<pre>BLK2_OFFSET := imm8[1:0]*32
|
|||
|
|
BLK1_OFFSET := imm8[2]*32
|
|||
|
|
SRC1_BYTE0 := SRC1[BLK1_OFFSET+7:BLK1_OFFSET]
|
|||
|
|
SRC1_BYTE1 := SRC1[BLK1_OFFSET+15:BLK1_OFFSET+8]
|
|||
|
|
SRC1_BYTE2 := SRC1[BLK1_OFFSET+23:BLK1_OFFSET+16]
|
|||
|
|
SRC1_BYTE3 := SRC1[BLK1_OFFSET+31:BLK1_OFFSET+24]
|
|||
|
|
SRC1_BYTE4 := SRC1[BLK1_OFFSET+39:BLK1_OFFSET+32]
|
|||
|
|
SRC1_BYTE5 := SRC1[BLK1_OFFSET+47:BLK1_OFFSET+40]
|
|||
|
|
SRC1_BYTE6 := SRC1[BLK1_OFFSET+55:BLK1_OFFSET+48]
|
|||
|
|
SRC1_BYTE7 := SRC1[BLK1_OFFSET+63:BLK1_OFFSET+56]
|
|||
|
|
SRC1_BYTE8 := SRC1[BLK1_OFFSET+71:BLK1_OFFSET+64]
|
|||
|
|
SRC1_BYTE9 := SRC1[BLK1_OFFSET+79:BLK1_OFFSET+72]
|
|||
|
|
SRC1_BYTE10 := SRC1[BLK1_OFFSET+87:BLK1_OFFSET+80]
|
|||
|
|
SRC2_BYTE0 := SRC2[BLK2_OFFSET+7:BLK2_OFFSET]
|
|||
|
|
SRC2_BYTE1 := SRC2[BLK2_OFFSET+15:BLK2_OFFSET+8]
|
|||
|
|
SRC2_BYTE2 := SRC2[BLK2_OFFSET+23:BLK2_OFFSET+16]
|
|||
|
|
SRC2_BYTE3 := SRC2[BLK2_OFFSET+31:BLK2_OFFSET+24]
|
|||
|
|
TEMP0 := ABS(SRC1_BYTE0 - SRC2_BYTE0)
|
|||
|
|
TEMP1 := ABS(SRC1_BYTE1 - SRC2_BYTE1)
|
|||
|
|
TEMP2 := ABS(SRC1_BYTE2 - SRC2_BYTE2)
|
|||
|
|
TEMP3 := ABS(SRC1_BYTE3 - SRC2_BYTE3)
|
|||
|
|
DEST[15:0] := TEMP0 + TEMP1 + TEMP2 + TEMP3
|
|||
|
|
TEMP0 := ABS(SRC1_BYTE1 - SRC2_BYTE0)
|
|||
|
|
TEMP1 := ABS(SRC1_BYTE2 - SRC2_BYTE1)
|
|||
|
|
TEMP2 := ABS(SRC1_BYTE3 - SRC2_BYTE2)
|
|||
|
|
TEMP3 := ABS(SRC1_BYTE4 - SRC2_BYTE3)
|
|||
|
|
DEST[31:16] := TEMP0 + TEMP1 + TEMP2 + TEMP3
|
|||
|
|
TEMP0 := ABS(SRC1_BYTE2 - SRC2_BYTE0)
|
|||
|
|
TEMP1 := ABS(SRC1_BYTE3 - SRC2_BYTE1)
|
|||
|
|
TEMP2 := ABS(SRC1_BYTE4 - SRC2_BYTE2)
|
|||
|
|
TEMP3 := ABS(SRC1_BYTE5 - SRC2_BYTE3)
|
|||
|
|
DEST[47:32] := TEMP0 + TEMP1 + TEMP2 + TEMP3
|
|||
|
|
TEMP0 := ABS(SRC1_BYTE3 - SRC2_BYTE0)
|
|||
|
|
TEMP1 := ABS(SRC1_BYTE4 - SRC2_BYTE1)
|
|||
|
|
TEMP2 := ABS(SRC1_BYTE5 - SRC2_BYTE2)
|
|||
|
|
TEMP3 := ABS(SRC1_BYTE6 - SRC2_BYTE3)
|
|||
|
|
DEST[63:48] := TEMP0 + TEMP1 + TEMP2 + TEMP3
|
|||
|
|
TEMP0 := ABS(SRC1_BYTE4 - SRC2_BYTE0)
|
|||
|
|
TEMP1 := ABS(SRC1_BYTE5 - SRC2_BYTE1)
|
|||
|
|
TEMP2 := ABS(SRC1_BYTE6 - SRC2_BYTE2)
|
|||
|
|
TEMP3 := ABS(SRC1_BYTE7 - SRC2_BYTE3)
|
|||
|
|
DEST[79:64] := TEMP0 + TEMP1 + TEMP2 + TEMP3
|
|||
|
|
TEMP0 := ABS(SRC1_BYTE5 - SRC2_BYTE0)
|
|||
|
|
TEMP1 := ABS(SRC1_BYTE6 - SRC2_BYTE1)
|
|||
|
|
TEMP2 := ABS(SRC1_BYTE7 - SRC2_BYTE2)
|
|||
|
|
TEMP3 := ABS(SRC1_BYTE8 - SRC2_BYTE3)
|
|||
|
|
DEST[95:80] := TEMP0 + TEMP1 + TEMP2 + TEMP3
|
|||
|
|
TEMP0 := ABS(SRC1_BYTE6 - SRC2_BYTE0)
|
|||
|
|
TEMP1 := ABS(SRC1_BYTE7 - SRC2_BYTE1)
|
|||
|
|
TEMP2 := ABS(SRC1_BYTE8 - SRC2_BYTE2)
|
|||
|
|
TEMP3 := ABS(SRC1_BYTE9 - SRC2_BYTE3)
|
|||
|
|
DEST[111:96] := TEMP0 + TEMP1 + TEMP2 + TEMP3
|
|||
|
|
TEMP0 := ABS(SRC1_BYTE7 - SRC2_BYTE0)
|
|||
|
|
TEMP1 := ABS(SRC1_BYTE8 - SRC2_BYTE1)
|
|||
|
|
TEMP2 := ABS(SRC1_BYTE9 - SRC2_BYTE2)
|
|||
|
|
TEMP3 := ABS(SRC1_BYTE10 - SRC2_BYTE3)
|
|||
|
|
DEST[127:112] := TEMP0 + TEMP1 + TEMP2 + TEMP3
|
|||
|
|
BLK2_OFFSET := imm8[4:3]*32 + 128
|
|||
|
|
BLK1_OFFSET := imm8[5]*32 + 128
|
|||
|
|
SRC1_BYTE0 := SRC1[BLK1_OFFSET+7:BLK1_OFFSET]
|
|||
|
|
SRC1_BYTE1 := SRC1[BLK1_OFFSET+15:BLK1_OFFSET+8]
|
|||
|
|
SRC1_BYTE2 := SRC1[BLK1_OFFSET+23:BLK1_OFFSET+16]
|
|||
|
|
SRC1_BYTE3 := SRC1[BLK1_OFFSET+31:BLK1_OFFSET+24]
|
|||
|
|
SRC1_BYTE4 := SRC1[BLK1_OFFSET+39:BLK1_OFFSET+32]
|
|||
|
|
SRC1_BYTE5 := SRC1[BLK1_OFFSET+47:BLK1_OFFSET+40]
|
|||
|
|
SRC1_BYTE6 := SRC1[BLK1_OFFSET+55:BLK1_OFFSET+48]
|
|||
|
|
SRC1_BYTE7 := SRC1[BLK1_OFFSET+63:BLK1_OFFSET+56]
|
|||
|
|
SRC1_BYTE8 := SRC1[BLK1_OFFSET+71:BLK1_OFFSET+64]
|
|||
|
|
SRC1_BYTE9 := SRC1[BLK1_OFFSET+79:BLK1_OFFSET+72]
|
|||
|
|
SRC1_BYTE10 := SRC1[BLK1_OFFSET+87:BLK1_OFFSET+80]
|
|||
|
|
SRC2_BYTE0 := SRC2[BLK2_OFFSET+7:BLK2_OFFSET]
|
|||
|
|
SRC2_BYTE1 := SRC2[BLK2_OFFSET+15:BLK2_OFFSET+8]
|
|||
|
|
SRC2_BYTE2 := SRC2[BLK2_OFFSET+23:BLK2_OFFSET+16]
|
|||
|
|
SRC2_BYTE3 := SRC2[BLK2_OFFSET+31:BLK2_OFFSET+24]
|
|||
|
|
TEMP0 := ABS(SRC1_BYTE0 - SRC2_BYTE0)
|
|||
|
|
TEMP1 := ABS(SRC1_BYTE1 - SRC2_BYTE1)
|
|||
|
|
TEMP2 := ABS(SRC1_BYTE2 - SRC2_BYTE2)
|
|||
|
|
TEMP3 := ABS(SRC1_BYTE3 - SRC2_BYTE3)
|
|||
|
|
DEST[143:128] := TEMP0 + TEMP1 + TEMP2 + TEMP3
|
|||
|
|
TEMP0 := ABS(SRC1_BYTE1 - SRC2_BYTE0)
|
|||
|
|
TEMP1 := ABS(SRC1_BYTE2 - SRC2_BYTE1)
|
|||
|
|
TEMP2 := ABS(SRC1_BYTE3 - SRC2_BYTE2)
|
|||
|
|
TEMP3 := ABS(SRC1_BYTE4 - SRC2_BYTE3)
|
|||
|
|
DEST[159:144] := TEMP0 + TEMP1 + TEMP2 + TEMP3
|
|||
|
|
TEMP0 := ABS(SRC1_BYTE2 - SRC2_BYTE0)
|
|||
|
|
TEMP1 := ABS(SRC1_BYTE3 - SRC2_BYTE1)
|
|||
|
|
TEMP2 := ABS(SRC1_BYTE4 - SRC2_BYTE2)
|
|||
|
|
TEMP3 := ABS(SRC1_BYTE5 - SRC2_BYTE3)
|
|||
|
|
DEST[175:160] := TEMP0 + TEMP1 + TEMP2 + TEMP3
|
|||
|
|
TEMP0 := ABS(SRC1_BYTE3 - SRC2_BYTE0)
|
|||
|
|
TEMP1 := ABS(SRC1_BYTE4 - SRC2_BYTE1)
|
|||
|
|
TEMP2 := ABS(SRC1_BYTE5 - SRC2_BYTE2)
|
|||
|
|
TEMP3 := ABS(SRC1_BYTE6 - SRC2_BYTE3)
|
|||
|
|
DEST[191:176] := TEMP0 + TEMP1 + TEMP2 + TEMP3
|
|||
|
|
TEMP0 := ABS(SRC1_BYTE4 - SRC2_BYTE0)
|
|||
|
|
TEMP1 := ABS(SRC1_BYTE5 - SRC2_BYTE1)
|
|||
|
|
TEMP2 := ABS(SRC1_BYTE6 - SRC2_BYTE2)
|
|||
|
|
TEMP3 := ABS(SRC1_BYTE7 - SRC2_BYTE3)
|
|||
|
|
DEST[207:192] := TEMP0 + TEMP1 + TEMP2 + TEMP3
|
|||
|
|
TEMP0 := ABS(SRC1_BYTE5 - SRC2_BYTE0)
|
|||
|
|
TEMP1 := ABS(SRC1_BYTE6 - SRC2_BYTE1)
|
|||
|
|
TEMP2 := ABS(SRC1_BYTE7 - SRC2_BYTE2)
|
|||
|
|
TEMP3 := ABS(SRC1_BYTE8 - SRC2_BYTE3)
|
|||
|
|
DEST[223:208] := TEMP0 + TEMP1 + TEMP2 + TEMP3
|
|||
|
|
TEMP0 := ABS(SRC1_BYTE6 - SRC2_BYTE0)
|
|||
|
|
TEMP1 := ABS(SRC1_BYTE7 - SRC2_BYTE1)
|
|||
|
|
TEMP2 := ABS(SRC1_BYTE8 - SRC2_BYTE2)
|
|||
|
|
TEMP3 := ABS(SRC1_BYTE9 - SRC2_BYTE3)
|
|||
|
|
DEST[239:224] := TEMP0 + TEMP1 + TEMP2 + TEMP3
|
|||
|
|
TEMP0 := ABS(SRC1_BYTE7 - SRC2_BYTE0)
|
|||
|
|
TEMP1 := ABS(SRC1_BYTE8 - SRC2_BYTE1)
|
|||
|
|
TEMP2 := ABS(SRC1_BYTE9 - SRC2_BYTE2)
|
|||
|
|
TEMP3 := ABS(SRC1_BYTE10 - SRC2_BYTE3)
|
|||
|
|
DEST[255:240] := TEMP0 + TEMP1 + TEMP2 + TEMP3
|
|||
|
|
</pre>
|
|||
|
|
<h3 id="vmpsadbw--vex-128-encoded-version-">VMPSADBW (VEX.128 Encoded Version)<a class="anchor" href="#vmpsadbw--vex-128-encoded-version-">
|
|||
|
|
¶
|
|||
|
|
</a></h3>
|
|||
|
|
<pre>BLK2_OFFSET := imm8[1:0]*32
|
|||
|
|
BLK1_OFFSET := imm8[2]*32
|
|||
|
|
SRC1_BYTE0 := SRC1[BLK1_OFFSET+7:BLK1_OFFSET]
|
|||
|
|
SRC1_BYTE1 := SRC1[BLK1_OFFSET+15:BLK1_OFFSET+8]
|
|||
|
|
SRC1_BYTE2 := SRC1[BLK1_OFFSET+23:BLK1_OFFSET+16]
|
|||
|
|
SRC1_BYTE3 := SRC1[BLK1_OFFSET+31:BLK1_OFFSET+24]
|
|||
|
|
SRC1_BYTE4 := SRC1[BLK1_OFFSET+39:BLK1_OFFSET+32]
|
|||
|
|
SRC1_BYTE5 := SRC1[BLK1_OFFSET+47:BLK1_OFFSET+40]
|
|||
|
|
SRC1_BYTE6 := SRC1[BLK1_OFFSET+55:BLK1_OFFSET+48]
|
|||
|
|
SRC1_BYTE7 := SRC1[BLK1_OFFSET+63:BLK1_OFFSET+56]
|
|||
|
|
SRC1_BYTE8 := SRC1[BLK1_OFFSET+71:BLK1_OFFSET+64]
|
|||
|
|
SRC1_BYTE9 := SRC1[BLK1_OFFSET+79:BLK1_OFFSET+72]
|
|||
|
|
SRC1_BYTE10 := SRC1[BLK1_OFFSET+87:BLK1_OFFSET+80]
|
|||
|
|
SRC2_BYTE0 := SRC2[BLK2_OFFSET+7:BLK2_OFFSET]
|
|||
|
|
SRC2_BYTE1 := SRC2[BLK2_OFFSET+15:BLK2_OFFSET+8]
|
|||
|
|
SRC2_BYTE2 := SRC2[BLK2_OFFSET+23:BLK2_OFFSET+16]
|
|||
|
|
SRC2_BYTE3 := SRC2[BLK2_OFFSET+31:BLK2_OFFSET+24]
|
|||
|
|
TEMP0 := ABS(SRC1_BYTE0 - SRC2_BYTE0)
|
|||
|
|
TEMP1 := ABS(SRC1_BYTE1 - SRC2_BYTE1)
|
|||
|
|
TEMP2 := ABS(SRC1_BYTE2 - SRC2_BYTE2)
|
|||
|
|
TEMP3 := ABS(SRC1_BYTE3 - SRC2_BYTE3)
|
|||
|
|
DEST[15:0] := TEMP0 + TEMP1 + TEMP2 + TEMP3
|
|||
|
|
TEMP0 := ABS(SRC1_BYTE1 - SRC2_BYTE0)
|
|||
|
|
TEMP1 := ABS(SRC1_BYTE2 - SRC2_BYTE1)
|
|||
|
|
TEMP2 := ABS(SRC1_BYTE3 - SRC2_BYTE2)
|
|||
|
|
TEMP3 := ABS(SRC1_BYTE4 - SRC2_BYTE3)
|
|||
|
|
DEST[31:16] := TEMP0 + TEMP1 + TEMP2 + TEMP3
|
|||
|
|
TEMP0 := ABS(SRC1_BYTE2 - SRC2_BYTE0)
|
|||
|
|
TEMP1 := ABS(SRC1_BYTE3 - SRC2_BYTE1)
|
|||
|
|
TEMP2 := ABS(SRC1_BYTE4 - SRC2_BYTE2)
|
|||
|
|
TEMP3 := ABS(SRC1_BYTE5 - SRC2_BYTE3)
|
|||
|
|
DEST[47:32] := TEMP0 + TEMP1 + TEMP2 + TEMP3
|
|||
|
|
TEMP0 := ABS(SRC1_BYTE3 - SRC2_BYTE0)
|
|||
|
|
TEMP1 := ABS(SRC1_BYTE4 - SRC2_BYTE1)
|
|||
|
|
TEMP2 := ABS(SRC1_BYTE5 - SRC2_BYTE2)
|
|||
|
|
TEMP3 := ABS(SRC1_BYTE6 - SRC2_BYTE3)
|
|||
|
|
DEST[63:48] := TEMP0 + TEMP1 + TEMP2 + TEMP3
|
|||
|
|
TEMP0 := ABS(SRC1_BYTE4 - SRC2_BYTE0)
|
|||
|
|
TEMP1 := ABS(SRC1_BYTE5 - SRC2_BYTE1)
|
|||
|
|
TEMP2 := ABS(SRC1_BYTE6 - SRC2_BYTE2)
|
|||
|
|
TEMP3 := ABS(SRC1_BYTE7 - SRC2_BYTE3)
|
|||
|
|
DEST[79:64] := TEMP0 + TEMP1 + TEMP2 + TEMP3
|
|||
|
|
TEMP0 := ABS(SRC1_BYTE5 - SRC2_BYTE0)
|
|||
|
|
TEMP1 := ABS(SRC1_BYTE6 - SRC2_BYTE1)
|
|||
|
|
TEMP2 := ABS(SRC1_BYTE7 - SRC2_BYTE2)
|
|||
|
|
TEMP3 := ABS(SRC1_BYTE8 - SRC2_BYTE3)
|
|||
|
|
DEST[95:80] := TEMP0 + TEMP1 + TEMP2 + TEMP3
|
|||
|
|
TEMP0 := ABS(SRC1_BYTE6 - SRC2_BYTE0)
|
|||
|
|
TEMP1 := ABS(SRC1_BYTE7 - SRC2_BYTE1)
|
|||
|
|
TEMP2 := ABS(SRC1_BYTE8 - SRC2_BYTE2)
|
|||
|
|
TEMP3 := ABS(SRC1_BYTE9 - SRC2_BYTE3)
|
|||
|
|
DEST[111:96] := TEMP0 + TEMP1 + TEMP2 + TEMP3
|
|||
|
|
TEMP0 := ABS(SRC1_BYTE7 - SRC2_BYTE0)
|
|||
|
|
TEMP1 := ABS(SRC1_BYTE8 - SRC2_BYTE1)
|
|||
|
|
TEMP2 := ABS(SRC1_BYTE9 - SRC2_BYTE2)
|
|||
|
|
TEMP3 := ABS(SRC1_BYTE10 - SRC2_BYTE3)
|
|||
|
|
DEST[127:112] := TEMP0 + TEMP1 + TEMP2 + TEMP3
|
|||
|
|
DEST[MAXVL-1:128] := 0
|
|||
|
|
</pre>
|
|||
|
|
<h3 id="mpsadbw--128-bit-legacy-sse-version-">MPSADBW (128-bit Legacy SSE Version)<a class="anchor" href="#mpsadbw--128-bit-legacy-sse-version-">
|
|||
|
|
¶
|
|||
|
|
</a></h3>
|
|||
|
|
<pre>SRC_OFFSET := imm8[1:0]*32
|
|||
|
|
DEST_OFFSET := imm8[2]*32
|
|||
|
|
DEST_BYTE0 := DEST[DEST_OFFSET+7:DEST_OFFSET]
|
|||
|
|
DEST_BYTE1 := DEST[DEST_OFFSET+15:DEST_OFFSET+8]
|
|||
|
|
DEST_BYTE2 := DEST[DEST_OFFSET+23:DEST_OFFSET+16]
|
|||
|
|
DEST_BYTE3 := DEST[DEST_OFFSET+31:DEST_OFFSET+24]
|
|||
|
|
DEST_BYTE4 := DEST[DEST_OFFSET+39:DEST_OFFSET+32]
|
|||
|
|
DEST_BYTE5 := DEST[DEST_OFFSET+47:DEST_OFFSET+40]
|
|||
|
|
DEST_BYTE6 := DEST[DEST_OFFSET+55:DEST_OFFSET+48]
|
|||
|
|
DEST_BYTE7 := DEST[DEST_OFFSET+63:DEST_OFFSET+56]
|
|||
|
|
DEST_BYTE8 := DEST[DEST_OFFSET+71:DEST_OFFSET+64]
|
|||
|
|
DEST_BYTE9 := DEST[DEST_OFFSET+79:DEST_OFFSET+72]
|
|||
|
|
DEST_BYTE10 := DEST[DEST_OFFSET+87:DEST_OFFSET+80]
|
|||
|
|
SRC_BYTE0 := SRC[SRC_OFFSET+7:SRC_OFFSET]
|
|||
|
|
SRC_BYTE1 := SRC[SRC_OFFSET+15:SRC_OFFSET+8]
|
|||
|
|
SRC_BYTE2 := SRC[SRC_OFFSET+23:SRC_OFFSET+16]
|
|||
|
|
SRC_BYTE3 := SRC[SRC_OFFSET+31:SRC_OFFSET+24]
|
|||
|
|
TEMP0 := ABS( DEST_BYTE0 - SRC_BYTE0)
|
|||
|
|
TEMP1 := ABS( DEST_BYTE1 - SRC_BYTE1)
|
|||
|
|
TEMP2 := ABS( DEST_BYTE2 - SRC_BYTE2)
|
|||
|
|
TEMP3 := ABS( DEST_BYTE3 - SRC_BYTE3)
|
|||
|
|
DEST[15:0] := TEMP0 + TEMP1 + TEMP2 + TEMP3
|
|||
|
|
TEMP0 := ABS( DEST_BYTE1 - SRC_BYTE0)
|
|||
|
|
TEMP1 := ABS( DEST_BYTE2 - SRC_BYTE1)
|
|||
|
|
TEMP2 := ABS( DEST_BYTE3 - SRC_BYTE2)
|
|||
|
|
TEMP3 := ABS( DEST_BYTE4 - SRC_BYTE3)
|
|||
|
|
DEST[31:16] := TEMP0 + TEMP1 + TEMP2 + TEMP3
|
|||
|
|
TEMP0 := ABS( DEST_BYTE2 - SRC_BYTE0)
|
|||
|
|
TEMP1 := ABS( DEST_BYTE3 - SRC_BYTE1)
|
|||
|
|
TEMP2 := ABS( DEST_BYTE4 - SRC_BYTE2)
|
|||
|
|
TEMP3 := ABS( DEST_BYTE5 - SRC_BYTE3)
|
|||
|
|
DEST[47:32] := TEMP0 + TEMP1 + TEMP2 + TEMP3
|
|||
|
|
TEMP0 := ABS( DEST_BYTE3 - SRC_BYTE0)
|
|||
|
|
TEMP1 := ABS( DEST_BYTE4 - SRC_BYTE1)
|
|||
|
|
TEMP2 := ABS( DEST_BYTE5 - SRC_BYTE2)
|
|||
|
|
TEMP3 := ABS( DEST_BYTE6 - SRC_BYTE3)
|
|||
|
|
DEST[63:48] := TEMP0 + TEMP1 + TEMP2 + TEMP3
|
|||
|
|
TEMP0 := ABS( DEST_BYTE4 - SRC_BYTE0)
|
|||
|
|
TEMP1 := ABS( DEST_BYTE5 - SRC_BYTE1)
|
|||
|
|
TEMP2 := ABS( DEST_BYTE6 - SRC_BYTE2)
|
|||
|
|
TEMP3 := ABS( DEST_BYTE7 - SRC_BYTE3)
|
|||
|
|
DEST[79:64] := TEMP0 + TEMP1 + TEMP2 + TEMP3
|
|||
|
|
TEMP0 := ABS( DEST_BYTE5 - SRC_BYTE0)
|
|||
|
|
TEMP1 := ABS( DEST_BYTE6 - SRC_BYTE1)
|
|||
|
|
TEMP2 := ABS( DEST_BYTE7 - SRC_BYTE2)
|
|||
|
|
TEMP3 := ABS( DEST_BYTE8 - SRC_BYTE3)
|
|||
|
|
DEST[95:80] := TEMP0 + TEMP1 + TEMP2 + TEMP3
|
|||
|
|
TEMP0 := ABS( DEST_BYTE6 - SRC_BYTE0)
|
|||
|
|
TEMP1 := ABS( DEST_BYTE7 - SRC_BYTE1)
|
|||
|
|
TEMP2 := ABS( DEST_BYTE8 - SRC_BYTE2)
|
|||
|
|
TEMP3 := ABS( DEST_BYTE9 - SRC_BYTE3)
|
|||
|
|
DEST[111:96] := TEMP0 + TEMP1 + TEMP2 + TEMP3
|
|||
|
|
TEMP0 := ABS( DEST_BYTE7 - SRC_BYTE0)
|
|||
|
|
TEMP1 := ABS( DEST_BYTE8 - SRC_BYTE1)
|
|||
|
|
TEMP2 := ABS( DEST_BYTE9 - SRC_BYTE2)
|
|||
|
|
TEMP3 := ABS( DEST_BYTE10 - SRC_BYTE3)
|
|||
|
|
DEST[127:112] := TEMP0 + TEMP1 + TEMP2 + TEMP3
|
|||
|
|
DEST[MAXVL-1:128] (Unmodified)
|
|||
|
|
</pre>
|
|||
|
|
<h2 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
|
|||
|
|
¶
|
|||
|
|
</a></h2>
|
|||
|
|
<pre>(V)MPSADBW __m128i _mm_mpsadbw_epu8 (__m128i s1, __m128i s2, const int mask);
|
|||
|
|
</pre>
|
|||
|
|
<pre>VMPSADBW __m256i _mm256_mpsadbw_epu8 (__m256i s1, __m256i s2, const int mask);
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</pre>
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<h2 id="flags-affected">Flags Affected<a class="anchor" href="#flags-affected">
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¶
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</a></h2>
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<p>None.</p>
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<h2 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
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|
¶
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</a></h2>
|
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<p>See <span class="not-imported">Table 2-21</span>, “Type 4 Class Exception Conditions.”</p><footer><p>
|
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|
|
This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
|
|||
|
|
inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
|
|||
|
|
ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
|
|||
|
|
</p></footer></body></html>
|