forked from NRZCode/ia32-64
279 lines
11 KiB
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279 lines
11 KiB
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>MOVD/MOVQ
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— Move Doubleword/Move Quadword</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>MOVD/MOVQ
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— Move Doubleword/Move Quadword</h1>
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<table>
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<tr>
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<th>Opcode/Instruction</th>
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<th>Op/ En</th>
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<th>64/32-bit Mode</th>
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<th>CPUID Feature Flag</th>
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<th>Description</th></tr>
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<tr>
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<td>NP 0F 6E /r MOVD mm, r/m32</td>
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<td>A</td>
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<td>V/V</td>
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<td>MMX</td>
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<td>Move doubleword from r/m32 to mm.</td></tr>
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<tr>
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<td>NP REX.W + 0F 6E /r MOVQ mm, r/m64</td>
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<td>A</td>
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<td>V/N.E.</td>
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<td>MMX</td>
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<td>Move quadword from r/m64 to mm.</td></tr>
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<tr>
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<td>NP 0F 7E /r MOVD r/m32, mm</td>
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<td>B</td>
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<td>V/V</td>
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<td>MMX</td>
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<td>Move doubleword from mm to r/m32.</td></tr>
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<tr>
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<td>NP REX.W + 0F 7E /r MOVQ r/m64, mm</td>
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<td>B</td>
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<td>V/N.E.</td>
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<td>MMX</td>
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<td>Move quadword from mm to r/m64.</td></tr>
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<tr>
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<td>66 0F 6E /r MOVD xmm, r/m32</td>
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<td>A</td>
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<td>V/V</td>
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<td>SSE2</td>
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<td>Move doubleword from r/m32 to xmm.</td></tr>
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<tr>
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<td>66 REX.W 0F 6E /r MOVQ xmm, r/m64</td>
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<td>A</td>
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<td>V/N.E.</td>
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<td>SSE2</td>
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<td>Move quadword from r/m64 to xmm.</td></tr>
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<tr>
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<td>66 0F 7E /r MOVD r/m32, xmm</td>
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<td>B</td>
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<td>V/V</td>
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<td>SSE2</td>
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<td>Move doubleword from xmm register to r/m32.</td></tr>
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<tr>
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<td>66 REX.W 0F 7E /r MOVQ r/m64, xmm</td>
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<td>B</td>
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<td>V/N.E.</td>
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<td>SSE2</td>
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<td>Move quadword from xmm register to r/m64.</td></tr>
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<tr>
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<td>VEX.128.66.0F.W0 6E / VMOVD xmm1, r32/m32</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX</td>
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<td>Move doubleword from r/m32 to xmm1.</td></tr>
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<tr>
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<td>VEX.128.66.0F.W1 6E /r VMOVQ xmm1, r64/m64</td>
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<td>A</td>
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<td>V/N.E<sup>1</sup>.</td>
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<td>AVX</td>
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<td>Move quadword from r/m64 to xmm1.</td></tr>
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<tr>
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<td>VEX.128.66.0F.W0 7E /r VMOVD r32/m32, xmm1</td>
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<td>B</td>
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<td>V/V</td>
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<td>AVX</td>
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<td>Move doubleword from xmm1 register to r/m32.</td></tr>
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<tr>
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<td>VEX.128.66.0F.W1 7E /r VMOVQ r64/m64, xmm1</td>
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<td>B</td>
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<td>V/N.E<sup>1</sup>.</td>
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<td>AVX</td>
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<td>Move quadword from xmm1 register to r/m64.</td></tr>
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<tr>
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<td>EVEX.128.66.0F.W0 6E /r VMOVD xmm1, r32/m32</td>
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<td>C</td>
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<td>V/V</td>
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<td>AVX512F</td>
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<td>Move doubleword from r/m32 to xmm1.</td></tr>
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<tr>
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<td>EVEX.128.66.0F.W1 6E /r VMOVQ xmm1, r64/m64</td>
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<td>C</td>
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<td>V/N.E.<sup>1</sup></td>
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<td>AVX512F</td>
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<td>Move quadword from r/m64 to xmm1.</td></tr>
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<tr>
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<td>EVEX.128.66.0F.W0 7E /r VMOVD r32/m32, xmm1</td>
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<td>D</td>
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<td>V/V</td>
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<td>AVX512F</td>
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<td>Move doubleword from xmm1 register to r/m32.</td></tr>
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<tr>
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<td>EVEX.128.66.0F.W1 7E /r VMOVQ r64/m64, xmm1</td>
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<td>D</td>
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<td>V/N.E.<sup>1</sup></td>
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<td>AVX512F</td>
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<td>Move quadword from xmm1 register to r/m64.</td></tr></table>
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<blockquote>
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<p>1. For this specific instruction, VEX.W/EVEX.W in non-64 bit is ignored; the instruction behaves as if the W0 version is used.</p></blockquote>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Tuple Type</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Operand 3</th>
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<th>Operand 4</th></tr>
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<tr>
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<td>A</td>
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<td>N/A</td>
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<td>ModRM:reg (w)</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td>
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<td>N/A</td></tr>
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<tr>
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<td>B</td>
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<td>N/A</td>
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<td>ModRM:r/m (w)</td>
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<td>ModRM:reg (r)</td>
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<td>N/A</td>
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<td>N/A</td></tr>
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<tr>
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<td>C</td>
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<td>Tuple1 Scalar</td>
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<td>ModRM:reg (w)</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td>
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<td>N/A</td></tr>
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<tr>
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<td>D</td>
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<td>Tuple1 Scalar</td>
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<td>ModRM:r/m (w)</td>
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<td>ModRM:reg (r)</td>
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<td>N/A</td>
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<td>N/A</td></tr></table>
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<h2 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h2>
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<p>Copies a doubleword from the source operand (second operand) to the destination operand (first operand). The source and destination operands can be general-purpose registers, MMX technology registers, XMM registers, or 32-bit memory locations. This instruction can be used to move a doubleword to and from the low doubleword of an MMX technology register and a general-purpose register or a 32-bit memory location, or to and from the low doubleword of an XMM register and a general-purpose register or a 32-bit memory location. The instruction cannot be used to transfer data between MMX technology registers, between XMM registers, between general-purpose registers, or between memory locations.</p>
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<p>When the destination operand is an MMX technology register, the source operand is written to the low doubleword of the register, and the register is zero-extended to 64 bits. When the destination operand is an XMM register, the source operand is written to the low doubleword of the register, and the register is zero-extended to 128 bits.</p>
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<p>In 64-bit mode, the instruction’s default operation size is 32 bits. Use of the REX.R prefix permits access to additional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits. See the summary chart at the beginning of this section for encoding data and limits.</p>
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<p>MOVD/Q with XMM destination:</p>
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<p>Moves a dword/qword integer from the source operand and stores it in the low 32/64-bits of the destination XMM register. The upper bits of the destination are zeroed. The source operand can be a 32/64-bit register or 32/64-bit memory location.</p>
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<p>128-bit Legacy SSE version: Bits (MAXVL-1:128) of the corresponding YMM destination register remain unchanged. Qword operation requires the use of REX.W=1.</p>
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<p>VEX.128 encoded version: Bits (MAXVL-1:128) of the destination register are zeroed. Qword operation requires the use of VEX.W=1.</p>
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<p>EVEX.128 encoded version: Bits (MAXVL-1:128) of the destination register are zeroed. Qword operation requires the use of EVEX.W=1.</p>
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<p>MOVD/Q with 32/64 reg/mem destination:</p>
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<p>Stores the low dword/qword of the source XMM register to 32/64-bit memory location or general-purpose register. Qword operation requires the use of REX.W=1, VEX.W=1, or EVEX.W=1.</p>
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<p>Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.</p>
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<p>If VMOVD or VMOVQ is encoded with VEX.L= 1, an attempt to execute the instruction encoded with VEX.L= 1 will cause an #UD exception.</p>
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<h2 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h2>
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<h3 id="movd--when-destination-operand-is-an-mmx-technology-register-">MOVD (When Destination Operand is an MMX Technology Register)<a class="anchor" href="#movd--when-destination-operand-is-an-mmx-technology-register-">
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¶
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</a></h3>
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<pre>DEST[31:0] := SRC;
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DEST[63:32] := 00000000H;
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</pre>
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<h3 id="movd--when-destination-operand-is-an-xmm-register-">MOVD (When Destination Operand is an XMM Register)<a class="anchor" href="#movd--when-destination-operand-is-an-xmm-register-">
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¶
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</a></h3>
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<pre>DEST[31:0] := SRC;
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DEST[127:32] := 000000000000000000000000H;
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DEST[MAXVL-1:128] (Unmodified)
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</pre>
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<h3 id="movd--when-source-operand-is-an-mmx-technology-or-xmm-register-">MOVD (When Source Operand is an MMX Technology or XMM Register)<a class="anchor" href="#movd--when-source-operand-is-an-mmx-technology-or-xmm-register-">
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¶
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</a></h3>
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<pre>DEST := SRC[31:0];
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</pre>
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<h3 id="vmovd--vex-encoded-version-when-destination-is-an-xmm-register-">VMOVD (VEX-Encoded Version when Destination is an XMM Register)<a class="anchor" href="#vmovd--vex-encoded-version-when-destination-is-an-xmm-register-">
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¶
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</a></h3>
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<pre>DEST[31:0] := SRC[31:0]
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DEST[MAXVL-1:32] := 0
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</pre>
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<h3 id="movq--when-destination-operand-is-an-xmm-register-">MOVQ (When Destination Operand is an XMM Register)<a class="anchor" href="#movq--when-destination-operand-is-an-xmm-register-">
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¶
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</a></h3>
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<pre>DEST[63:0] := SRC[63:0];
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DEST[127:64] := 0000000000000000H;
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DEST[MAXVL-1:128] (Unmodified)
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</pre>
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<h3 id="movq--when-destination-operand-is-r-m64-">MOVQ (When Destination Operand is r/m64)<a class="anchor" href="#movq--when-destination-operand-is-r-m64-">
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¶
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</a></h3>
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<pre>DEST[63:0] := SRC[63:0];
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</pre>
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<h3 id="movq--when-source-operand-is-an-xmm-register-or-r-m64-">MOVQ (When Source Operand is an XMM Register or r/m64)<a class="anchor" href="#movq--when-source-operand-is-an-xmm-register-or-r-m64-">
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¶
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</a></h3>
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<pre>DEST := SRC[63:0];
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</pre>
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<h3 id="vmovq--vex-encoded-version-when-destination-is-an-xmm-register-">VMOVQ (VEX-Encoded Version When Destination is an XMM Register)<a class="anchor" href="#vmovq--vex-encoded-version-when-destination-is-an-xmm-register-">
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¶
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</a></h3>
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<pre>DEST[63:0] := SRC[63:0]
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DEST[MAXVL-1:64] := 0
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</pre>
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<h3 id="vmovd--evex-encoded-version-when-destination-is-an-xmm-register-">VMOVD (EVEX-Encoded Version When Destination is an XMM Register)<a class="anchor" href="#vmovd--evex-encoded-version-when-destination-is-an-xmm-register-">
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¶
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</a></h3>
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<pre>DEST[31:0] := SRC[31:0]
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DEST[MAXVL-1:32] := 0
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</pre>
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<h3 id="vmovq--evex-encoded-version-when-destination-is-an-xmm-register-">VMOVQ (EVEX-Encoded Version When Destination is an XMM Register)<a class="anchor" href="#vmovq--evex-encoded-version-when-destination-is-an-xmm-register-">
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¶
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</a></h3>
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<pre>DEST[63:0] := SRC[63:0]
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DEST[MAXVL-1:64] := 0
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</pre>
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<h2 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
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¶
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</a></h2>
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<pre>MOVD __m64 _mm_cvtsi32_si64 (int i )
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</pre>
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<pre>MOVD int _mm_cvtsi64_si32 ( __m64m )
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</pre>
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<pre>MOVD __m128i _mm_cvtsi32_si128 (int a)
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</pre>
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<pre>MOVD int _mm_cvtsi128_si32 ( __m128i a)
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</pre>
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<pre>MOVQ __int64 _mm_cvtsi128_si64(__m128i);
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</pre>
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<pre>MOVQ __m128i _mm_cvtsi64_si128(__int64);
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</pre>
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<pre>VMOVD __m128i _mm_cvtsi32_si128( int);
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</pre>
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<pre>VMOVD int _mm_cvtsi128_si32( __m128i );
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</pre>
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<pre>VMOVQ __m128i _mm_cvtsi64_si128 (__int64);
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</pre>
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<pre>VMOVQ __int64 _mm_cvtsi128_si64(__m128i );
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</pre>
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<pre>VMOVQ __m128i _mm_loadl_epi64( __m128i * s);
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</pre>
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<pre>VMOVQ void _mm_storel_epi64( __m128i * d, __m128i s);
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</pre>
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<h2 id="flags-affected">Flags Affected<a class="anchor" href="#flags-affected">
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¶
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</a></h2>
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<p>None.</p>
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<h2 class="exceptions" id="simd-floating-point-exceptions">SIMD Floating-Point Exceptions<a class="anchor" href="#simd-floating-point-exceptions">
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¶
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</a></h2>
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<p>None.</p>
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<h2 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
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¶
|
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</a></h2>
|
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<p>Non-EVEX-encoded instruction, see <span class="not-imported">Table 2-22</span>, “Type 5 Class Exception Conditions.”</p>
|
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|
|
<p>EVEX-encoded instruction, see <span class="not-imported">Table 2-57</span>, “Type E9NF Class Exception Conditions.”</p>
|
|||
|
|
<p>Additionally:</p>
|
|||
|
|
<table>
|
|||
|
|
<tr>
|
|||
|
|
<td rowspan="2">#UD</td>
|
|||
|
|
<td>If VEX.L = 1.</td></tr>
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|||
|
|
<tr>
|
|||
|
|
<td>If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.</td></tr></table><footer><p>
|
|||
|
|
This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
|
|||
|
|
inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
|
|||
|
|
ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
|
|||
|
|
</p></footer></body></html>
|