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250 lines
9.7 KiB
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>IDIV
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— Signed Divide</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>IDIV
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— Signed Divide</h1>
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<table>
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<tr>
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<th>Opcode</th>
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<th>Instruction</th>
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<th>Op/En</th>
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<th>64-Bit Mode</th>
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<th>Compat/Leg Mode</th>
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<th>Description</th></tr>
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<tr>
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<td>F6 /7</td>
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<td>IDIV r/m8</td>
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<td>M</td>
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<td>Valid</td>
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<td>Valid</td>
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<td>Signed divide AX by r/m8, with result stored in: AL := Quotient, AH := Remainder.</td></tr>
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<tr>
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<td>REX + F6 /7</td>
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<td>IDIV r/m8<sup>1</sup></td>
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<td>M</td>
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<td>Valid</td>
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<td>N.E.</td>
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<td>Signed divide AX by r/m8, with result stored in AL := Quotient, AH := Remainder.</td></tr>
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<tr>
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<td>F7 /7</td>
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<td>IDIV r/m16</td>
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<td>M</td>
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<td>Valid</td>
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<td>Valid</td>
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<td>Signed divide DX:AX by r/m16, with result stored in AX := Quotient, DX := Remainder.</td></tr>
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<tr>
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<td>F7 /7</td>
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<td>IDIV r/m32</td>
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<td>M</td>
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<td>Valid</td>
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<td>Valid</td>
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<td>Signed divide EDX:EAX by r/m32, with result stored in EAX := Quotient, EDX := Remainder.</td></tr>
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<tr>
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<td>REX.W + F7 /7</td>
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<td>IDIV r/m64</td>
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<td>M</td>
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<td>Valid</td>
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<td>N.E.</td>
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<td>Signed divide RDX:RAX by r/m64, with result stored in RAX := Quotient, RDX := Remainder.</td></tr></table>
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<blockquote>
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<p>1. In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.</p></blockquote>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Operand 3</th>
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<th>Operand 4</th></tr>
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<tr>
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<td>M</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td>
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<td>N/A</td>
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<td>N/A</td></tr></table>
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<h2 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h2>
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<p>Divides the (signed) value in the AX, DX:AX, or EDX:EAX (dividend) by the source operand (divisor) and stores the result in the AX (AH:AL), DX:AX, or EDX:EAX registers. The source operand can be a general-purpose register or a memory location. The action of this instruction depends on the operand size (dividend/divisor).</p>
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<p>Non-integral results are truncated (chopped) towards 0. The remainder is always less than the divisor in magnitude. Overflow is indicated with the #DE (divide error) exception rather than with the CF flag.</p>
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<p>In 64-bit mode, the instruction’s default operation size is 32 bits. Use of the REX.R prefix permits access to additional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits. In 64-bit mode when REX.W is applied, the instruction divides the signed value in RDX:RAX by the source operand. RAX contains a 64-bit quotient; RDX contains a 64-bit remainder.</p>
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<p>See the summary chart at the beginning of this section for encoding data and limits. See <a href='idiv.html#tbl-3-51'>Table 3-51</a>.</p>
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<figure id="tbl-3-51">
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<table>
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<tr>
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<th>Operand Size</th>
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<th>Dividend</th>
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<th>Divisor</th>
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<th>Quotient</th>
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<th>Remainder</th>
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<th>Quotient Range</th></tr>
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<tr>
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<td>Word/byte Doubleword/word Quadword/doubleword Doublequadword/ quadword</td>
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<td>AX DX:AX EDX:EAX RDX:RAX</td>
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<td>r/m8 r/m16 r/m32 r/m64</td>
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<td>AL AX EAX RAX</td>
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<td>AH DX EDX RDX</td>
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<td>−128 to +127 −32,768 to +32,767 −2<sup>31</sup> to 2<sup>31</sup> − 1 −2<sup>63</sup> to 2<sup>63</sup> − 1</td></tr></table>
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<figcaption><a href='idiv.html#tbl-3-51'>Table 3-51</a>. IDIV Results</figcaption></figure>
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<h2 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h2>
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<pre>IF SRC = 0
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THEN #DE; (* Divide error *)
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FI;
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IF OperandSize = 8 (* Word/byte operation *)
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THEN
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temp := AX / SRC; (* Signed division *)
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IF (temp > 7FH) or (temp < 80H)
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(* If a positive result is greater than 7FH or a negative result is less than 80H *)
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THEN #DE; (* Divide error *)
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ELSE
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AL := temp;
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AH := AX SignedModulus SRC;
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FI;
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ELSE IF OperandSize = 16 (* Doubleword/word operation *)
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THEN
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temp := DX:AX / SRC; (* Signed division *)
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IF (temp > 7FFFH) or (temp < 8000H)
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(* If a positive result is greater than 7FFFH
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or a negative result is less than 8000H *)
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THEN
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#DE; (* Divide error *)
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ELSE
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AX := temp;
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DX := DX:AX SignedModulus SRC;
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FI;
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FI;
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ELSE IF OperandSize = 32 (* Quadword/doubleword operation *)
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temp := EDX:EAX / SRC; (* Signed division *)
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IF (temp > 7FFFFFFFH) or (temp < 80000000H)
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(* If a positive result is greater than 7FFFFFFFH
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or a negative result is less than 80000000H *)
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THEN
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#DE; (* Divide error *)
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ELSE
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EAX := temp;
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EDX := EDXE:AX SignedModulus SRC;
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FI;
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FI;
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ELSE IF OperandSize = 64 (* Doublequadword/quadword operation *)
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temp := RDX:RAX / SRC; (* Signed division *)
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IF (temp > 7FFFFFFFFFFFFFFFH) or (temp < 8000000000000000H)
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(* If a positive result is greater than 7FFFFFFFFFFFFFFFH
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or a negative result is less than 8000000000000000H *)
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THEN
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#DE; (* Divide error *)
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ELSE
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RAX := temp;
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RDX := RDE:RAX SignedModulus SRC;
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FI;
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FI;
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FI;
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</pre>
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<h2 id="flags-affected">Flags Affected<a class="anchor" href="#flags-affected">
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¶
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</a></h2>
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<p>The CF, OF, SF, ZF, AF, and PF flags are undefined.</p>
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<h2 class="exceptions" id="protected-mode-exceptions">Protected Mode Exceptions<a class="anchor" href="#protected-mode-exceptions">
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¶
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</a></h2>
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<table>
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<tr>
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<td rowspan="2">#DE</td>
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<td>If the source operand (divisor) is 0.</td></tr>
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<tr>
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<td>The signed result (quotient) is too large for the destination.</td></tr>
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<tr>
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<td rowspan="2">#GP(0)</td>
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<td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
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<tr>
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<td>If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment selector.</td></tr>
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<tr>
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<td>#SS(0)</td>
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<td>If a memory operand effective address is outside the SS segment limit.</td></tr>
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<tr>
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<td>#PF(fault-code)</td>
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<td>If a page fault occurs.</td></tr>
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<tr>
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<td>#AC(0)</td>
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<td>If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.</td></tr>
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<tr>
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<td>#UD</td>
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<td>If the LOCK prefix is used.</td></tr></table>
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<h2 class="exceptions" id="real-address-mode-exceptions">Real-Address Mode Exceptions<a class="anchor" href="#real-address-mode-exceptions">
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¶
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</a></h2>
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<table>
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<tr>
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<td rowspan="2">#DE</td>
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<td>If the source operand (divisor) is 0.</td></tr>
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<tr>
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<td>The signed result (quotient) is too large for the destination.</td></tr>
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<tr>
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<td>#GP</td>
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<td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
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<tr>
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<td>#SS</td>
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<td>If a memory operand effective address is outside the SS segment limit.</td></tr>
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<tr>
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<td>#UD</td>
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<td>If the LOCK prefix is used.</td></tr></table>
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<h2 class="exceptions" id="virtual-8086-mode-exceptions">Virtual-8086 Mode Exceptions<a class="anchor" href="#virtual-8086-mode-exceptions">
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¶
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</a></h2>
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<table>
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<tr>
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<td rowspan="2">#DE</td>
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<td>If the source operand (divisor) is 0.</td></tr>
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<tr>
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<td>The signed result (quotient) is too large for the destination.</td></tr>
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<tr>
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<td>#GP(0)</td>
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<td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
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<tr>
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<td>#SS(0)</td>
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<td>If a memory operand effective address is outside the SS segment limit.</td></tr>
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<tr>
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<td>#PF(fault-code)</td>
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<td>If a page fault occurs.</td></tr>
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<tr>
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<td>#AC(0)</td>
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<td>If alignment checking is enabled and an unaligned memory reference is made.</td></tr>
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<tr>
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<td>#UD</td>
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<td>If the LOCK prefix is used.</td></tr></table>
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<h2 class="exceptions" id="compatibility-mode-exceptions">Compatibility Mode Exceptions<a class="anchor" href="#compatibility-mode-exceptions">
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¶
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</a></h2>
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<p>Same exceptions as in protected mode.</p>
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<h2 class="exceptions" id="64-bit-mode-exceptions">64-Bit Mode Exceptions<a class="anchor" href="#64-bit-mode-exceptions">
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¶
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</a></h2>
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<table>
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<tr>
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<td>#SS(0)</td>
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<td>If a memory address referencing the SS segment is in a non-canonical form.</td></tr>
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<tr>
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<td>#GP(0)</td>
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<td>If the memory address is in a non-canonical form.</td></tr>
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<tr>
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<td rowspan="2">#DE</td>
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<td>If the source operand (divisor) is 0</td></tr>
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<tr>
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<td>If the quotient is too large for the designated register.</td></tr>
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<tr>
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<td>#PF(fault-code)</td>
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<td>If a page fault occurs.</td></tr>
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<tr>
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<td>#AC(0)</td>
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<td>If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.</td></tr>
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<tr>
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<td>#UD</td>
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<td>If the LOCK prefix is used.</td></tr></table><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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