forked from NRZCode/ia32-64
111 lines
4.4 KiB
HTML
111 lines
4.4 KiB
HTML
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<!DOCTYPE html>
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>F2XM1
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— Compute 2x–1</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>F2XM1
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— Compute 2x–1</h1>
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<table>
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<tr>
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<th>Opcode </th>
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<th></th>
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<th>Mode</th>
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<th>Leg Mode</th>
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<th>Description</th></tr>
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<tr>
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<td>D9 F0 </td>
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<td></td>
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<td></td>
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<td></td>
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<td>Replace ST(0) with (2<sup>ST(0)</sup> – 1).</td></tr></table>
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<h2 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h2>
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<p>Computes the exponential value of 2 to the power of the source operand minus 1. The source operand is located in register ST(0) and the result is also stored in ST(0). The value of the source operand must lie in the range –1.0 to +1.0. If the source value is outside this range, the result is undefined.</p>
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<p>The following table shows the results obtained when computing the exponential value of various classes of numbers, assuming that neither overflow nor underflow occurs.</p>
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<figure id="tbl-3-16">
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<table>
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<tr>
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<th>ST(0) SRC</th>
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<th>ST(0) DEST</th></tr>
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<tr>
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<td>− 1.0 to −0</td>
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<td>− 0.5 to − 0</td></tr>
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<tr>
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<td>−0</td>
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<td>−0</td></tr>
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<tr>
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<td>+0</td>
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<td>+0</td></tr>
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<tr>
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<td>+ 0 to +1.0</td>
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<td>+ 0 to 1.0</td></tr></table>
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<figcaption><a href='f2xm1.html#tbl-3-16'>Table 3-16</a>. Results Obtained from F2XM1</figcaption></figure>
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<p>Values other than 2 can be exponentiated using the following formula:</p>
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<p><sub>x</sub>y <sub>:= 2</sub>(y ∗ log<sub>2</sub>x)</p>
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<p>This instruction’s operation is the same in non-64-bit modes and 64-bit mode.</p>
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<h2 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h2>
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<pre>ST(0) := (2<sup>ST(0)</sup> − 1);
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</pre>
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<h2 id="fpu-flags-affected">FPU Flags Affected<a class="anchor" href="#fpu-flags-affected">
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¶
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</a></h2>
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<table>
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<tr>
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<td rowspan="2">C1</td>
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<td>Set to 0 if stack underflow occurred.</td></tr>
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<tr>
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<td>Set if result was rounded up; cleared otherwise.</td></tr>
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<tr>
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<td>C0, C2, C3</td>
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<td>Undefined.</td></tr></table>
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<h2 class="exceptions" id="floating-point-exceptions">Floating-Point Exceptions<a class="anchor" href="#floating-point-exceptions">
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¶
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</a></h2>
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<table>
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<tr>
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<td>#IS</td>
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<td>Stack underflow occurred.</td></tr>
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<tr>
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<td>#IA</td>
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<td>Source operand is an SNaN value or unsupported format.</td></tr>
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<tr>
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<td>#D</td>
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<td>Source is a denormal value.</td></tr>
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<tr>
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<td>#U</td>
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<td>Result is too small for destination format.</td></tr>
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<tr>
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<td>#P</td>
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<td>Value cannot be represented exactly in destination format.</td></tr></table>
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<h2 class="exceptions" id="protected-mode-exceptions">Protected Mode Exceptions<a class="anchor" href="#protected-mode-exceptions">
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¶
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</a></h2>
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<table>
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<tr>
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<td>#NM</td>
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<td>CR0.EM[bit 2] or CR0.TS[bit 3] = 1.</td></tr>
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<tr>
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<td>#UD</td>
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<td>If the LOCK prefix is used.</td></tr></table>
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<h2 class="exceptions" id="real-address-mode-exceptions">Real-Address Mode Exceptions<a class="anchor" href="#real-address-mode-exceptions">
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¶
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</a></h2>
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<p>Same exceptions as in protected mode.</p>
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<h2 class="exceptions" id="virtual-8086-mode-exceptions">Virtual-8086 Mode Exceptions<a class="anchor" href="#virtual-8086-mode-exceptions">
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¶
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</a></h2>
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<p>Same exceptions as in protected mode.</p>
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<h2 class="exceptions" id="compatibility-mode-exceptions">Compatibility Mode Exceptions<a class="anchor" href="#compatibility-mode-exceptions">
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¶
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</a></h2>
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<p>Same exceptions as in protected mode.</p>
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<h2 class="exceptions" id="64-bit-mode-exceptions">64-Bit Mode Exceptions<a class="anchor" href="#64-bit-mode-exceptions">
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¶
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</a></h2>
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<p>Same exceptions as in protected mode.</p><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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