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143 lines
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>CVTSS2SI
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— Convert Scalar Single Precision Floating-Point Value to Doubleword Integer</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>CVTSS2SI
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— Convert Scalar Single Precision Floating-Point Value to Doubleword Integer</h1>
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<table>
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<tr>
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<th>Opcode/Instruction</th>
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<th>Op / En</th>
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<th>64/32 bit Mode Support</th>
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<th>CPUID Feature Flag</th>
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<th>Description</th></tr>
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<tr>
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<td>F3 0F 2D /r CVTSS2SI r32, xmm1/m32</td>
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<td>A</td>
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<td>V/V</td>
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<td>SSE</td>
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<td>Convert one single precision floating-point value from xmm1/m32 to one signed doubleword integer in r32.</td></tr>
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<tr>
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<td>F3 REX.W 0F 2D /r CVTSS2SI r64, xmm1/m32</td>
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<td>A</td>
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<td>V/N.E.</td>
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<td>SSE</td>
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<td>Convert one single precision floating-point value from xmm1/m32 to one signed quadword integer in r64.</td></tr>
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<tr>
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<td>VEX.LIG.F3.0F.W0 2D /r <sup>1</sup> VCVTSS2SI r32, xmm1/m32</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX</td>
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<td>Convert one single precision floating-point value from xmm1/m32 to one signed doubleword integer in r32.</td></tr>
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<tr>
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<td>VEX.LIG.F3.0F.W1 2D /r <sup>1</sup> VCVTSS2SI r64, xmm1/m32</td>
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<td>A</td>
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<td>V/N.E.<sup>2</sup></td>
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<td>AVX</td>
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<td>Convert one single precision floating-point value from xmm1/m32 to one signed quadword integer in r64.</td></tr>
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<tr>
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<td>EVEX.LLIG.F3.0F.W0 2D /r VCVTSS2SI r32, xmm1/m32{er}</td>
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<td>B</td>
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<td>V/V</td>
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<td>AVX512F</td>
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<td>Convert one single precision floating-point value from xmm1/m32 to one signed doubleword integer in r32.</td></tr>
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<tr>
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<td>EVEX.LLIG.F3.0F.W1 2D /r VCVTSS2SI r64, xmm1/m32{er}</td>
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<td>B</td>
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<td>V/N.E.<sup>2</sup></td>
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<td>AVX512F</td>
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<td>Convert one single precision floating-point value from xmm1/m32 to one signed quadword integer in r64.</td></tr></table>
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<blockquote>
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<p>1. Software should ensure VCVTSS2SI is encoded with VEX.L=0. Encoding VCVTSS2SI with VEX.L=1 may encounter unpredictable behavior across different processor generations.</p>
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<p>2. VEX.W1/EVEX.W1 in non-64 bit is ignored; the instructions behaves as if the W0 version is used.</p></blockquote>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Tuple Type</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Operand 3</th>
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<th>Operand 4</th></tr>
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<tr>
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<td>A</td>
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<td>N/A</td>
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<td>ModRM:reg (w)</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td>
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<td>N/A</td></tr>
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<tr>
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<td>B</td>
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<td>Tuple1 Fixed</td>
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<td>ModRM:reg (w)</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td>
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<td>N/A</td></tr></table>
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<h2 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h2>
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<p>Converts a single precision floating-point value in the source operand (the second operand) to a signed doubleword integer (or signed quadword integer if operand size is 64 bits) in the destination operand (the first operand). The source operand can be an XMM register or a memory location. The destination operand is a general-purpose register. When the source operand is an XMM register, the single precision floating-point value is contained in the low doubleword of the register.</p>
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<p>When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR register or the embedded rounding control bits. If a converted result cannot be represented in the destination format, the floating-point invalid exception is raised, and if this exception is masked, the indefinite integer value (2<sup>w</sup>-1, where w represents the number of bits in the destination format) is returned.</p>
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<p>Legacy SSE instructions: In 64-bit mode, Use of the REX.W prefix promotes the instruction to produce 64-bit data. See the summary chart at the beginning of this section for encoding data and limits.</p>
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<p>VEX.W1 and EVEX.W1 versions: promotes the instruction to produce 64-bit data in 64-bit mode.</p>
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<p>Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.</p>
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<p>Software should ensure VCVTSS2SI is encoded with VEX.L=0. Encoding VCVTSS2SI with VEX.L=1 may encounter unpredictable behavior across different processor generations.</p>
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<h2 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h2>
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<h3 id="vcvtss2si--evex-encoded-version-">VCVTSS2SI (EVEX Encoded Version)<a class="anchor" href="#vcvtss2si--evex-encoded-version-">
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¶
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</a></h3>
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<pre>IF (SRC *is register*) AND (EVEX.b = 1)
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THEN
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SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(EVEX.RC);
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ELSE
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SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(MXCSR.RC);
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FI;
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IF 64-bit Mode and OperandSize = 64
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THEN
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DEST[63:0] := Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0]);
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ELSE
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DEST[31:0] := Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0]);
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FI;
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</pre>
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<h3 id="-v-cvtss2si--legacy-and-vex-128-encoded-version-">(V)CVTSS2SI (Legacy and VEX.128 Encoded Version)<a class="anchor" href="#-v-cvtss2si--legacy-and-vex-128-encoded-version-">
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¶
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</a></h3>
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<pre>IF 64-bit Mode and OperandSize = 64
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THEN
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DEST[63:0] := Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0]);
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ELSE
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DEST[31:0] := Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0]);
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FI;
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</pre>
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<h2 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
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¶
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</a></h2>
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<pre>VCVTSS2SI int _mm_cvtss_i32( __m128 a);
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</pre>
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<pre>VCVTSS2SI int _mm_cvt_roundss_i32( __m128 a, int r);
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</pre>
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<pre>VCVTSS2SI __int64 _mm_cvtss_i64( __m128 a);
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</pre>
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<pre>VCVTSS2SI __int64 _mm_cvt_roundss_i64( __m128 a, int r);
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</pre>
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<h2 class="exceptions" id="simd-floating-point-exceptions">SIMD Floating-Point Exceptions<a class="anchor" href="#simd-floating-point-exceptions">
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¶
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</a></h2>
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<p>Invalid, Precision.</p>
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<h2 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
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¶
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</a></h2>
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<p>VEX-encoded instructions, see <span class="not-imported">Table 2-20</span>, “Type 3 Class Exception Conditions,” additionally:</p>
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<table>
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<tr>
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<td>#UD</td>
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<td>If VEX.vvvv != 1111B.</td></tr></table>
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<p>EVEX-encoded instructions, see <span class="not-imported">Table 2-48</span>, “Type E3NF Class Exception Conditions.”</p><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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