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113 lines
5.6 KiB
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>V4FMADDSS/V4FNMADDSS
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— Scalar Single Precision Floating-Point Fused Multiply-Add(4-Iterations)</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>V4FMADDSS/V4FNMADDSS
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— Scalar Single Precision Floating-Point Fused Multiply-Add(4-Iterations)</h1>
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<table>
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<tr>
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<th>Opcode/Instruction</th>
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<th>Op/En</th>
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<th>64/32 bit Mode Support</th>
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<th>CPUID Feature Flag</th>
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<th>Description</th></tr>
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<tr>
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<td>EVEX.LLIG.F2.0F38.W0 9B /r V4FMADDSS xmm1{k1}{z}, xmm2+3, m128</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX512_4FMAPS</td>
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<td>Multiply scalar single-precision floating-point values from source register block indicated by xmm2 by values from m128 and accumulate the result in xmm1.</td></tr>
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<tr>
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<td>EVEX.LLIG.F2.0F38.W0 AB /r V4FNMADDSS xmm1{k1}{z}, xmm2+3, m128</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX512_4FMAPS</td>
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<td>Multiply and negate scalar single-precision floating-point values from source register block indicated by xmm2 by values from m128 and accumulate the result in xmm1.</td></tr></table>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En Tuple Operand 1 Operand 2 Operand 3 Operand 4</th>
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<th></th>
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<th></th>
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<th></th>
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<th></th>
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<th></th></tr>
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<tr>
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<td>A Tuple1_4X ModRM:reg (r, w) EVEX.vvvv (r) ModRM:r/m (r) N/A</td>
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<td></td>
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<td></td>
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<td></td>
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<td></td>
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<td></td></tr></table>
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<h3 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h3>
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<p>This instruction computes 4 sequential scalar fused single-precision floating-point multiply-add instructions with a sequentially selected memory operand in each of the four steps.</p>
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<p>In the above box, the notation of “+3” is used to denote that the instruction accesses 4 source registers based that operand; sources are consecutive, start in a multiple of 4 boundary, and contain the encoded register operand.</p>
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<p>This instruction supports memory fault suppression. The entire memory operand is loaded if the least significant mask bit is set to 1 or if a “no masking” encoding is used.</p>
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<p>The tuple type Tuple1_4X implies that four 32-bit elements (16 bytes) are referenced by the memory operation portion of this instruction.</p>
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<p>Rounding is performed at every FMA boundary. Exceptions are also taken sequentially. Pre- and post-computational exceptions of the first FMA take priority over the pre- and post-computational exceptions of the second FMA, etc.</p>
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<h3 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h3>
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<pre>src_reg_id is the 5 bit index of the vector register specified in the instruction as the src1 register.
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define NFMA_SS(vl, dest, k1, msrc, regs_loaded, src_base, posneg):
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tmpdest := dest
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// reg[] is an array representing the SIMD register file.
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IF k1[0] or *no writemask*:
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FOR j := 0 to regs_loaded - 1:
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IF posneg = 0:
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tmpdest.single[0] := RoundFPControl_MXCSR(tmpdest.single[0] - reg[src_base + j ].single[0] * msrc.single[j])
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ELSE:
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tmpdest.single[0] := RoundFPControl_MXCSR(tmpdest.single[0] + reg[src_base + j ].single[0] * msrc.single[j])
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ELSE IF *zeroing*:
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tmpdest.single[0] := 0
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dest := tmpdst
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dest[MAX_VL-1:VL] := 0
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</pre>
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<h4 id="v4fmaddss-and-v4fnmaddss-dest-k1---src1--msrc--avx512-">V4FMADDSS and V4FNMADDSS dest{k1}, src1, msrc (AVX512)<a class="anchor" href="#v4fmaddss-and-v4fnmaddss-dest-k1---src1--msrc--avx512-">
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¶
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</a></h4>
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<pre>VL = 128
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regs_loaded := 4
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src_base := src_reg_id & ~3 // for src1 operand
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posneg := 0 if negative form, 1 otherwise
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NFMA_SS(vl, dest, k1, msrc, regs_loaded, src_base, posneg)
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</pre>
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<h3 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
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¶
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</a></h3>
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<pre>V4FMADDSS __m128 _mm_4fmadd_ss(__m128, __m128x4, __m128 *);
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</pre>
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<pre>V4FMADDSS __m128 _mm_mask_4fmadd_ss(__m128, __mmask8, __m128x4, __m128 *);
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</pre>
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<pre>V4FMADDSS __m128 _mm_maskz_4fmadd_ss(__mmask8, __m128, __m128x4, __m128 *);
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</pre>
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<pre>V4FNMADDSS __m128 _mm_4fnmadd_ss(__m128, __m128x4, __m128 *);
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</pre>
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<pre>V4FNMADDSS __m128 _mm_mask_4fnmadd_ss(__m128, __mmask8, __m128x4, __m128 *);
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</pre>
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<pre>V4FNMADDSS __m128 _mm_maskz_4fnmadd_ss(__mmask8, __m128, __m128x4, __m128 *);
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</pre>
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<h3 class="exceptions" id="simd-floating-point-exceptions">SIMD Floating-Point Exceptions<a class="anchor" href="#simd-floating-point-exceptions">
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¶
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</a></h3>
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<p>Overflow, Underflow, Invalid, Precision, Denormal.</p>
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<h3 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
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¶
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</a></h3>
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<p>See Type E2; additionally:</p>
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<table>
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<tr>
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<td>#UD</td>
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<td>If the EVEX broadcast bit is set to 1.</td></tr>
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<tr>
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<td>#UD</td>
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<td>If the MODRM.mod = 0b11.</td></tr></table><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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