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114 lines
5.3 KiB
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>UCOMISS
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— Unordered Compare Scalar Single Precision Floating-Point Values and Set EFLAGS</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>UCOMISS
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— Unordered Compare Scalar Single Precision Floating-Point Values and Set EFLAGS</h1>
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<table>
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<tr>
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<th>Opcode/Instruction</th>
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<th>Op / En</th>
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<th>64/32 bit Mode Support</th>
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<th>CPUID Feature Flag</th>
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<th>Description</th></tr>
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<tr>
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<td>NP 0F 2E /r UCOMISS xmm1, xmm2/m32</td>
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<td>A</td>
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<td>V/V</td>
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<td>SSE</td>
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<td>Compare low single precision floating-point values in xmm1 and xmm2/mem32 and set the EFLAGS flags accordingly.</td></tr>
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<tr>
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<td>VEX.LIG.0F.WIG 2E /r VUCOMISS xmm1, xmm2/m32</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX</td>
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<td>Compare low single precision floating-point values in xmm1 and xmm2/mem32 and set the EFLAGS flags accordingly.</td></tr>
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<tr>
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<td>EVEX.LLIG.0F.W0 2E /r VUCOMISS xmm1, xmm2/m32{sae}</td>
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<td>B</td>
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<td>V/V</td>
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<td>AVX512F</td>
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<td>Compare low single precision floating-point values in xmm1 and xmm2/mem32 and set the EFLAGS flags accordingly.</td></tr></table>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Tuple Type</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Operand 3</th>
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<th>Operand 4</th></tr>
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<tr>
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<td>A</td>
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<td>N/A</td>
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<td>ModRM:reg (r)</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td>
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<td>N/A</td></tr>
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<tr>
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<td>B</td>
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<td>Tuple1 Scalar</td>
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<td>ModRM:reg (w)</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td>
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<td>N/A</td></tr></table>
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<h2 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h2>
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<p>Compares the single precision floating-point values in the low doublewords of operand 1 (first operand) and operand 2 (second operand), and sets the ZF, PF, and CF flags in the EFLAGS register according to the result (unordered, greater than, less than, or equal). The OF, SF, and AF flags in the EFLAGS register are set to 0. The unordered result is returned if either source operand is a NaN (QNaN or SNaN).</p>
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<p>Operand 1 is an XMM register; operand 2 can be an XMM register or a 32 bit memory location.</p>
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<p>The UCOMISS instruction differs from the COMISS instruction in that it signals a SIMD floating-point invalid operation exception (#I) only if a source operand is an SNaN. The COMISS instruction signals an invalid operation exception when a source operand is either a QNaN or SNaN.</p>
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<p>The EFLAGS register is not updated if an unmasked SIMD floating-point exception is generated.</p>
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<p>Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.</p>
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<p>Software should ensure VCOMISS is encoded with VEX.L=0. Encoding VCOMISS with VEX.L=1 may encounter unpredictable behavior across different processor generations.</p>
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<h2 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h2>
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<h3 id="-v-ucomiss--all-versions-">(V)UCOMISS (All Versions)<a class="anchor" href="#-v-ucomiss--all-versions-">
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¶
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</a></h3>
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<pre>RESULT := UnorderedCompare(DEST[31:0] <> SRC[31:0]) {
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(* Set EFLAGS *) CASE (RESULT) OF
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UNORDERED: ZF,PF,CF := 111;
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GREATER_THAN: ZF,PF,CF := 000;
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LESS_THAN: ZF,PF,CF := 001;
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EQUAL: ZF,PF,CF := 100;
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ESAC;
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OF, AF, SF := 0; }
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</pre>
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<h2 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
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¶
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</a></h2>
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<pre>VUCOMISS int _mm_comi_round_ss(__m128 a, __m128 b, int imm, int sae);
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</pre>
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<pre>UCOMISS int _mm_ucomieq_ss(__m128 a, __m128 b);
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</pre>
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<pre>UCOMISS int _mm_ucomilt_ss(__m128 a, __m128 b);
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</pre>
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<pre>UCOMISS int _mm_ucomile_ss(__m128 a, __m128 b);
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</pre>
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<pre>UCOMISS int _mm_ucomigt_ss(__m128 a, __m128 b);
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</pre>
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<pre>UCOMISS int _mm_ucomige_ss(__m128 a, __m128 b);
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</pre>
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<pre>UCOMISS int _mm_ucomineq_ss(__m128 a, __m128 b);
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</pre>
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<h2 class="exceptions" id="simd-floating-point-exceptions">SIMD Floating-Point Exceptions<a class="anchor" href="#simd-floating-point-exceptions">
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¶
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</a></h2>
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<p>Invalid (if SNaN Operands), Denormal.</p>
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<h2 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
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¶
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</a></h2>
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<p>VEX-encoded instructions, see <span class="not-imported">Table 2-20</span>, “Type 3 Class Exception Conditions,” additionally:</p>
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<table>
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<tr>
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<td>#UD</td>
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<td>If VEX.vvvv != 1111B.</td></tr></table>
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<p>EVEX-encoded instructions, see <span class="not-imported">Table 2-48</span>, “Type E3NF Class Exception Conditions.”</p><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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