forked from NRZCode/ia32-64
92 lines
4.3 KiB
HTML
92 lines
4.3 KiB
HTML
|
<!DOCTYPE html>
|
|||
|
|
<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>RSM
|
|||
|
|
— Resume From System Management Mode</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>RSM
|
|||
|
|
— Resume From System Management Mode</h1>
|
|||
|
|
|
|||
|
|
<table>
|
|||
|
|
<tr>
|
|||
|
|
<th>Opcode*</th>
|
|||
|
|
<th>Instruction</th>
|
|||
|
|
<th>Op/En</th>
|
|||
|
|
<th>64-Bit Mode</th>
|
|||
|
|
<th>Compat/Leg Mode</th>
|
|||
|
|
<th>Description</th></tr>
|
|||
|
|
<tr>
|
|||
|
|
<td>0F AA</td>
|
|||
|
|
<td>RSM</td>
|
|||
|
|
<td>ZO</td>
|
|||
|
|
<td>Valid</td>
|
|||
|
|
<td>Valid</td>
|
|||
|
|
<td>Resume operation of interrupted program.</td></tr></table>
|
|||
|
|
<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
|
|||
|
|
¶
|
|||
|
|
</a></h2>
|
|||
|
|
<table>
|
|||
|
|
<tr>
|
|||
|
|
<th>Op/En</th>
|
|||
|
|
<th>Operand 1</th>
|
|||
|
|
<th>Operand 2</th>
|
|||
|
|
<th>Operand 3</th>
|
|||
|
|
<th>Operand 4</th></tr>
|
|||
|
|
<tr>
|
|||
|
|
<td>ZO</td>
|
|||
|
|
<td>N/A</td>
|
|||
|
|
<td>N/A</td>
|
|||
|
|
<td>N/A</td>
|
|||
|
|
<td>N/A</td></tr></table>
|
|||
|
|
<h2 id="description">Description<a class="anchor" href="#description">
|
|||
|
|
¶
|
|||
|
|
</a></h2>
|
|||
|
|
<p>Returns program control from system management mode (SMM) to the application program or operating-system procedure that was interrupted when the processor received an SMM interrupt. The processor’s state is restored from the dump created upon entering SMM. If the processor detects invalid state information during state restoration, it enters the shutdown state. The following invalid information can cause a shutdown:</p>
|
|||
|
|
<ul>
|
|||
|
|
<li>Any reserved bit of CR4 is set to 1.</li>
|
|||
|
|
<li>Any illegal combination of bits in CR0, such as (PG=1 and PE=0) or (NW=1 and CD=0).</li>
|
|||
|
|
<li>(Intel Pentium and Intel486TM processors only.) The value stored in the state dump base field is not a 32-KByte aligned address.</li></ul>
|
|||
|
|
<p>The contents of the model-specific registers are not affected by a return from SMM.</p>
|
|||
|
|
<p>The SMM state map used by RSM supports resuming processor context for non-64-bit modes and 64-bit mode.</p>
|
|||
|
|
<p>See Chapter 32, “System Management Mode,” in the Intel<sup>®</sup> 64 and IA-32 Architectures Software Developer’s Manual, Volume 3C, for more information about SMM and the behavior of the RSM instruction.</p>
|
|||
|
|
<h2 id="operation">Operation<a class="anchor" href="#operation">
|
|||
|
|
¶
|
|||
|
|
</a></h2>
|
|||
|
|
<pre>ReturnFromSMM;
|
|||
|
|
IF (IA-32e mode supported) or (CPUID DisplayFamily_DisplayModel = 06H_0CH )
|
|||
|
|
THEN
|
|||
|
|
ProcessorState := Restore(SMMDump(IA-32e SMM STATE MAP));
|
|||
|
|
Else
|
|||
|
|
ProcessorState := Restore(SMMDump(Non-32-Bit-Mode SMM STATE MAP));
|
|||
|
|
FI
|
|||
|
|
</pre>
|
|||
|
|
<h2 id="flags-affected">Flags Affected<a class="anchor" href="#flags-affected">
|
|||
|
|
¶
|
|||
|
|
</a></h2>
|
|||
|
|
<p>All.</p>
|
|||
|
|
<h2 class="exceptions" id="protected-mode-exceptions">Protected Mode Exceptions<a class="anchor" href="#protected-mode-exceptions">
|
|||
|
|
¶
|
|||
|
|
</a></h2>
|
|||
|
|
<table>
|
|||
|
|
<tr>
|
|||
|
|
<td rowspan="2">#UD</td>
|
|||
|
|
<td>If an attempt is made to execute this instruction when the processor is not in SMM.</td></tr>
|
|||
|
|
<tr>
|
|||
|
|
<td>If the LOCK prefix is used.</td></tr></table>
|
|||
|
|
<h2 class="exceptions" id="real-address-mode-exceptions">Real-Address Mode Exceptions<a class="anchor" href="#real-address-mode-exceptions">
|
|||
|
|
¶
|
|||
|
|
</a></h2>
|
|||
|
|
<p>Same exceptions as in protected mode.</p>
|
|||
|
|
<h2 class="exceptions" id="virtual-8086-mode-exceptions">Virtual-8086 Mode Exceptions<a class="anchor" href="#virtual-8086-mode-exceptions">
|
|||
|
|
¶
|
|||
|
|
</a></h2>
|
|||
|
|
<p>Same exceptions as in protected mode.</p>
|
|||
|
|
<h2 class="exceptions" id="compatibility-mode-exceptions">Compatibility Mode Exceptions<a class="anchor" href="#compatibility-mode-exceptions">
|
|||
|
|
¶
|
|||
|
|
</a></h2>
|
|||
|
|
<p>Same exceptions as in protected mode.</p>
|
|||
|
|
<h2 class="exceptions" id="64-bit-mode-exceptions">64-Bit Mode Exceptions<a class="anchor" href="#64-bit-mode-exceptions">
|
|||
|
|
¶
|
|||
|
|
</a></h2>
|
|||
|
|
<p>Same exceptions as in protected mode.</p><footer><p>
|
|||
|
|
This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
|
|||
|
|
inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
|
|||
|
|
ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
|
|||
|
|
</p></footer></body></html>
|