forked from NRZCode/ia32-64
266 lines
12 KiB
HTML
266 lines
12 KiB
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>MOVAPS
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— Move Aligned Packed Single Precision Floating-Point Values</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>MOVAPS
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— Move Aligned Packed Single Precision Floating-Point Values</h1>
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<table>
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<tr>
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<th>Opcode/Instruction</th>
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<th>Op/En</th>
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<th>64/32 bit Mode Support</th>
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<th>CPUID Feature Flag</th>
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<th>Description</th></tr>
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<tr>
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<td>NP 0F 28 /r MOVAPS xmm1, xmm2/m128</td>
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<td>A</td>
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<td>V/V</td>
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<td>SSE</td>
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<td>Move aligned packed single precision floating-point values from xmm2/mem to xmm1.</td></tr>
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<tr>
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<td>NP 0F 29 /r MOVAPS xmm2/m128, xmm1</td>
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<td>B</td>
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<td>V/V</td>
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<td>SSE</td>
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<td>Move aligned packed single precision floating-point values from xmm1 to xmm2/mem.</td></tr>
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<tr>
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<td>VEX.128.0F.WIG 28 /r VMOVAPS xmm1, xmm2/m128</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX</td>
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<td>Move aligned packed single precision floating-point values from xmm2/mem to xmm1.</td></tr>
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<tr>
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<td>VEX.128.0F.WIG 29 /r VMOVAPS xmm2/m128, xmm1</td>
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<td>B</td>
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<td>V/V</td>
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<td>AVX</td>
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<td>Move aligned packed single precision floating-point values from xmm1 to xmm2/mem.</td></tr>
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<tr>
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<td>VEX.256.0F.WIG 28 /r VMOVAPS ymm1, ymm2/m256</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX</td>
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<td>Move aligned packed single precision floating-point values from ymm2/mem to ymm1.</td></tr>
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<tr>
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<td>VEX.256.0F.WIG 29 /r VMOVAPS ymm2/m256, ymm1</td>
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<td>B</td>
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<td>V/V</td>
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<td>AVX</td>
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<td>Move aligned packed single precision floating-point values from ymm1 to ymm2/mem.</td></tr>
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<tr>
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<td>EVEX.128.0F.W0 28 /r VMOVAPS xmm1 {k1}{z}, xmm2/m128</td>
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<td>C</td>
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<td>V/V</td>
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<td>AVX512VL AVX512F</td>
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<td>Move aligned packed single precision floating-point values from xmm2/m128 to xmm1 using writemask k1.</td></tr>
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<tr>
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<td>EVEX.256.0F.W0 28 /r VMOVAPS ymm1 {k1}{z}, ymm2/m256</td>
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<td>C</td>
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<td>V/V</td>
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<td>AVX512VL AVX512F</td>
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<td>Move aligned packed single precision floating-point values from ymm2/m256 to ymm1 using writemask k1.</td></tr>
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<tr>
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<td>EVEX.512.0F.W0 28 /r VMOVAPS zmm1 {k1}{z}, zmm2/m512</td>
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<td>C</td>
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<td>V/V</td>
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<td>AVX512F</td>
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<td>Move aligned packed single precision floating-point values from zmm2/m512 to zmm1 using writemask k1.</td></tr>
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<tr>
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<td>EVEX.128.0F.W0 29 /r VMOVAPS xmm2/m128 {k1}{z}, xmm1</td>
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<td>D</td>
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<td>V/V</td>
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<td>AVX512VL AVX512F</td>
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<td>Move aligned packed single precision floating-point values from xmm1 to xmm2/m128 using writemask k1.</td></tr>
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<tr>
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<td>EVEX.256.0F.W0 29 /r VMOVAPS ymm2/m256 {k1}{z}, ymm1</td>
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<td>D</td>
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<td>V/V</td>
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<td>AVX512VL AVX512F</td>
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<td>Move aligned packed single precision floating-point values from ymm1 to ymm2/m256 using writemask k1.</td></tr>
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<tr>
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<td>EVEX.512.0F.W0 29 /r VMOVAPS zmm2/m512 {k1}{z}, zmm1</td>
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<td>D</td>
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<td>V/V</td>
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<td>AVX512F</td>
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<td>Move aligned packed single precision floating-point values from zmm1 to zmm2/m512 using writemask k1.</td></tr></table>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Tuple Type</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Operand 3</th>
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<th>Operand 4</th></tr>
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<tr>
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<td>A</td>
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<td>N/A</td>
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<td>ModRM:reg (w)</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td>
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<td>N/A</td></tr>
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<tr>
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<td>B</td>
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<td>N/A</td>
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<td>ModRM:r/m (w)</td>
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<td>ModRM:reg (r)</td>
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<td>N/A</td>
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<td>N/A</td></tr>
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<tr>
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<td>C</td>
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<td>Full Mem</td>
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<td>ModRM:reg (w)</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td>
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<td>N/A</td></tr>
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<tr>
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<td>D</td>
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<td>Full Mem</td>
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<td>ModRM:r/m (w)</td>
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<td>ModRM:reg (r)</td>
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<td>N/A</td>
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<td>N/A</td></tr></table>
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<h2 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h2>
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<p>Moves 4, 8 or 16 single precision floating-point values from the source operand (second operand) to the destination operand (first operand). This instruction can be used to load an XMM, YMM or ZMM register from an 128-bit, 256-bit or 512-bit memory location, to store the contents of an XMM, YMM or ZMM register into a 128-bit, 256-bit or 512-bit memory location, or to move data between two XMM, two YMM or two ZMM registers.</p>
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<p>When the source or destination operand is a memory operand, the operand must be aligned on a 16-byte (128-bit version), 32-byte (VEX.256 encoded version) or 64-byte (EVEX.512 encoded version) boundary or a general-protection exception (#GP) will be generated. For EVEX.512 encoded versions, the operand must be aligned to the size of the memory operand. To move single precision floating-point values to and from unaligned memory locations, use the VMOVUPS instruction.</p>
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<p>Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.</p>
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<p>EVEX.512 encoded version:</p>
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<p>Moves 512 bits of packed single precision floating-point values from the source operand (second operand) to the destination operand (first operand). This instruction can be used to load a ZMM register from a 512-bit float32 memory location, to store the contents of a ZMM register into a float32 memory location, or to move data between two ZMM registers. When the source or destination operand is a memory operand, the operand must be aligned on a 64-byte boundary or a general-protection exception (#GP) will be generated. To move single precision floating-point values to and from unaligned memory locations, use the VMOVUPS instruction.</p>
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<p>VEX.256 and EVEX.256 encoded version:</p>
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<p>Moves 256 bits of packed single precision floating-point values from the source operand (second operand) to the destination operand (first operand). This instruction can be used to load a YMM register from a 256-bit memory location, to store the contents of a YMM register into a 256-bit memory location, or to move data between two YMM registers. When the source or destination operand is a memory operand, the operand must be aligned on a 32-byte boundary or a general-protection exception (#GP) will be generated.</p>
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<p>128-bit versions:</p>
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<p>Moves 128 bits of packed single precision floating-point values from the source operand (second operand) to the destination operand (first operand). This instruction can be used to load an XMM register from a 128-bit memory location, to store the contents of an XMM register into a 128-bit memory location, or to move data between two XMM registers. When the source or destination operand is a memory operand, the operand must be aligned on a 16-byte boundary or a general-protection exception (#GP) will be generated. To move single precision floating-point values to and from unaligned memory locations, use the VMOVUPS instruction.</p>
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<p>128-bit Legacy SSE version: Bits (MAXVL-1:128) of the corresponding ZMM destination register remain unchanged.</p>
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<p>(E)VEX.128 encoded version: Bits (MAXVL-1:128) of the destination ZMM register are zeroed.</p>
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<h2 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h2>
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<h3 id="vmovaps--evex-encoded-versions--register-copy-form-">VMOVAPS (EVEX Encoded Versions, Register-Copy Form)<a class="anchor" href="#vmovaps--evex-encoded-versions--register-copy-form-">
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¶
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</a></h3>
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<pre>(KL, VL) = (4, 128), (8, 256), (16, 512)
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FOR j := 0 TO KL-1
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i := j * 32
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IF k1[j] OR *no writemask*
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THEN DEST[i+31:i] := SRC[i+31:i]
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ELSE
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IF *merging-masking*
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THEN *DEST[i+31:i] remains unchanged*
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ELSE DEST[i+31:i] := 0 ; zeroing-masking
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FI
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FI;
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ENDFOR
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DEST[MAXVL-1:VL] := 0
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</pre>
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<h3 id="vmovaps--evex-encoded-versions--store-form-">VMOVAPS (EVEX Encoded Versions, Store Form)<a class="anchor" href="#vmovaps--evex-encoded-versions--store-form-">
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¶
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</a></h3>
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<pre>(KL, VL) = (4, 128), (8, 256), (16, 512)
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FOR j := 0 TO KL-1
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i := j * 32
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IF k1[j] OR *no writemask*
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THEN DEST[i+31:i] :=
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SRC[i+31:i]
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ELSE *DEST[i+31:i] remains unchanged*
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; merging-masking
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ENDFOR;
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</pre>
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<h3 id="vmovaps--evex-encoded-versions--load-form-">VMOVAPS (EVEX Encoded Versions, Load Form)<a class="anchor" href="#vmovaps--evex-encoded-versions--load-form-">
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¶
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</a></h3>
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<pre>(KL, VL) = (4, 128), (8, 256), (16, 512)
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FOR j := 0 TO KL-1
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i := j * 32
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IF k1[j] OR *no writemask*
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THEN DEST[i+31:i] := SRC[i+31:i]
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ELSE
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IF *merging-masking*
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THEN *DEST[i+31:i] remains unchanged*
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ELSE DEST[i+31:i] := 0 ; zeroing-masking
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FI
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FI;
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ENDFOR
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DEST[MAXVL-1:VL] := 0
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</pre>
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<h3 id="vmovaps--vex-256-encoded-version--load---and-register-copy-">VMOVAPS (VEX.256 Encoded Version, Load - and Register Copy)<a class="anchor" href="#vmovaps--vex-256-encoded-version--load---and-register-copy-">
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¶
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</a></h3>
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<pre>DEST[255:0] := SRC[255:0]
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DEST[MAXVL-1:256] := 0
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</pre>
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<h3 id="vmovaps--vex-256-encoded-version--store-form-">VMOVAPS (VEX.256 Encoded Version, Store-Form)<a class="anchor" href="#vmovaps--vex-256-encoded-version--store-form-">
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¶
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</a></h3>
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<pre>DEST[255:0] := SRC[255:0]
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</pre>
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<h3 id="vmovaps--vex-128-encoded-version--load---and-register-copy-">VMOVAPS (VEX.128 Encoded Version, Load - and Register Copy)<a class="anchor" href="#vmovaps--vex-128-encoded-version--load---and-register-copy-">
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¶
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</a></h3>
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<pre>DEST[127:0] := SRC[127:0]
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DEST[MAXVL-1:128] := 0
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</pre>
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<h3 id="movaps--128-bit-load--and-register-copy--form-legacy-sse-version-">MOVAPS (128-bit Load- and Register-Copy- Form Legacy SSE Version)<a class="anchor" href="#movaps--128-bit-load--and-register-copy--form-legacy-sse-version-">
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¶
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</a></h3>
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<pre>DEST[127:0] := SRC[127:0]
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DEST[MAXVL-1:128] (Unmodified)
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</pre>
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<h3 id="-v-movaps--128-bit-store-form-version-">(V)MOVAPS (128-bit Store-Form Version)<a class="anchor" href="#-v-movaps--128-bit-store-form-version-">
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¶
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</a></h3>
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<pre>DEST[127:0] := SRC[127:0]
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</pre>
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<h2 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
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¶
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</a></h2>
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<pre>VMOVAPS __m512 _mm512_load_ps( void * m);
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</pre>
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<pre>VMOVAPS __m512 _mm512_mask_load_ps(__m512 s, __mmask16 k, void * m);
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</pre>
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<pre>VMOVAPS __m512 _mm512_maskz_load_ps( __mmask16 k, void * m);
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</pre>
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<pre>VMOVAPS void _mm512_store_ps( void * d, __m512 a);
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</pre>
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<pre>VMOVAPS void _mm512_mask_store_ps( void * d, __mmask16 k, __m512 a);
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</pre>
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<pre>VMOVAPS __m256 _mm256_mask_load_ps(__m256 a, __mmask8 k, void * s);
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</pre>
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<pre>VMOVAPS __m256 _mm256_maskz_load_ps( __mmask8 k, void * s);
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</pre>
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<pre>VMOVAPS void _mm256_mask_store_ps( void * d, __mmask8 k, __m256 a);
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</pre>
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<pre>VMOVAPS __m128 _mm_mask_load_ps(__m128 a, __mmask8 k, void * s);
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</pre>
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<pre>VMOVAPS __m128 _mm_maskz_load_ps( __mmask8 k, void * s);
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</pre>
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<pre>VMOVAPS void _mm_mask_store_ps( void * d, __mmask8 k, __m128 a);
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</pre>
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<pre>MOVAPS __m256 _mm256_load_ps (float * p);
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</pre>
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<pre>MOVAPS void _mm256_store_ps(float * p, __m256 a);
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</pre>
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<pre>MOVAPS __m128 _mm_load_ps (float * p);
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</pre>
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<pre>MOVAPS void _mm_store_ps(float * p, __m128 a);
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</pre>
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<h2 class="exceptions" id="simd-floating-point-exceptions">SIMD Floating-Point Exceptions<a class="anchor" href="#simd-floating-point-exceptions">
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¶
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</a></h2>
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<p>None.</p>
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<h2 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
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¶
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</a></h2>
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<p>Non-EVEX-encoded instruction, see Exceptions Type1.SSE in <span class="not-imported">Table 2-18</span>, “Type 1 Class Exception Conditions,” additionally:</p>
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<table>
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<tr>
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<td>#UD</td>
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<td>If VEX.vvvv != 1111B.</td></tr></table>
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<p>EVEX-encoded instruction, see <span class="not-imported">Table 2-44</span>, “Type E1 Class Exception Conditions.”</p><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
|
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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