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102 lines
5.9 KiB
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102 lines
5.9 KiB
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>LDDQU
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— Load Unaligned Integer 128 Bits</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>LDDQU
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— Load Unaligned Integer 128 Bits</h1>
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<table>
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<tr>
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<th>Opcode/Instruction</th>
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<th>Op/En</th>
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<th>64/32-bit Mode</th>
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<th>CPUID Feature Flag</th>
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<th>Description</th></tr>
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<tr>
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<td>F2 0F F0 /r LDDQU xmm1, mem</td>
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<td>RM</td>
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<td>V/V</td>
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<td>SSE3</td>
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<td>Load unaligned data from mem and return double quadword in xmm1.</td></tr>
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<tr>
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<td>VEX.128.F2.0F.WIG F0 /r VLDDQU xmm1, m128</td>
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<td>RM</td>
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<td>V/V</td>
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<td>AVX</td>
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<td>Load unaligned packed integer values from mem to xmm1.</td></tr>
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<tr>
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<td>VEX.256.F2.0F.WIG F0 /r VLDDQU ymm1, m256</td>
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<td>RM</td>
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<td>V/V</td>
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<td>AVX</td>
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<td>Load unaligned packed integer values from mem to ymm1.</td></tr></table>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Operand 3</th>
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<th>Operand 4</th></tr>
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<tr>
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<td>RM</td>
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<td>ModRM:reg (w)</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td>
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<td>N/A</td></tr></table>
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<h2 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h2>
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<p>The instruction is <em>functionally similar</em> to (V)MOVDQU ymm/xmm, m256/m128 for loading from memory. That is: 32/16 bytes of data starting at an address specified by the source memory operand (second operand) are fetched from memory and placed in a destination register (first operand). The source operand need not be aligned on a 32/16-byte boundary. Up to 64/32 bytes may be loaded from memory; this is implementation dependent.</p>
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<p>This instruction may improve performance relative to (V)MOVDQU if the source operand crosses a cache line boundary. In situations that require the data loaded by (V)LDDQU be modified and stored to the same location, use (V)MOVDQU or (V)MOVDQA instead of (V)LDDQU. To move a double quadword to or from memory locations that are known to be aligned on 16-byte boundaries, use the (V)MOVDQA instruction.</p>
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<h2 id="implementation-notes">Implementation Notes<a class="anchor" href="#implementation-notes">
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¶
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</a></h2>
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<ul>
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<li>If the source is aligned to a 32/16-byte boundary, based on the implementation, the 32/16 bytes may be loaded more than once. For that reason, the usage of (V)LDDQU should be avoided when using uncached or write-combining (WC) memory regions. For uncached or WC memory regions, keep using (V)MOVDQU.</li>
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<li>This instruction is a replacement for (V)MOVDQU (load) in situations where cache line splits significantly affect performance. It should not be used in situations where store-load forwarding is performance critical. If performance of store-load forwarding is critical to the application, use (V)MOVDQA store-load pairs when data is 256/128-bit aligned or (V)MOVDQU store-load pairs when data is 256/128-bit unaligned.</li>
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<li>If the memory address is not aligned on 32/16-byte boundary, some implementations may load up to 64/32 bytes and return 32/16 bytes in the destination. Some processor implementations may issue multiple loads to access the appropriate 32/16 bytes. Developers of multi-threaded or multi-processor software should be aware that on these processors the loads will be performed in a non-atomic way.</li>
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<li>If alignment checking is enabled (CR0.AM = 1, RFLAGS.AC = 1, and CPL = 3), an alignment-check exception (#AC) may or may not be generated (depending on processor implementation) when the memory address is not aligned on an 8-byte boundary.</li></ul>
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<p>In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).</p>
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<p>Note: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.</p>
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<h2 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h2>
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<h3 id="lddqu--128-bit-legacy-sse-version-">LDDQU (128-bit Legacy SSE Version)<a class="anchor" href="#lddqu--128-bit-legacy-sse-version-">
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¶
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</a></h3>
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<pre>DEST[127:0] := SRC[127:0]
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DEST[MAXVL-1:128] (Unmodified)
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</pre>
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<h3 id="vlddqu--vex-128-encoded-version-">VLDDQU (VEX.128 Encoded Version)<a class="anchor" href="#vlddqu--vex-128-encoded-version-">
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¶
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</a></h3>
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<pre>DEST[127:0] := SRC[127:0]
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DEST[MAXVL-1:128] := 0
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</pre>
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<h3 id="vlddqu--vex-256-encoded-version-">VLDDQU (VEX.256 Encoded Version)<a class="anchor" href="#vlddqu--vex-256-encoded-version-">
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¶
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</a></h3>
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<pre>DEST[255:0] := SRC[255:0]
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</pre>
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<h2 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
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¶
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</a></h2>
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<pre>LDDQU __m128i _mm_lddqu_si128 (__m128i * p);
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</pre>
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<pre>VLDDQU __m256i _mm256_lddqu_si256 (__m256i * p);
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</pre>
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<h2 class="exceptions" id="numeric-exceptions">Numeric Exceptions<a class="anchor" href="#numeric-exceptions">
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¶
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</a></h2>
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<p>None.</p>
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<h2 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
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¶
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</a></h2>
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<p>See <span class="not-imported">Table 2-21</span>, “Type 4 Class Exception Conditions.”</p>
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<p>Note treatment of #AC varies.</p><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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