forked from NRZCode/ia32-64
118 lines
4.4 KiB
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118 lines
4.4 KiB
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>KSHIFTRW/KSHIFTRB/KSHIFTRQ/KSHIFTRD
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— Shift Right Mask Registers</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>KSHIFTRW/KSHIFTRB/KSHIFTRQ/KSHIFTRD
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— Shift Right Mask Registers</h1>
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<table>
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<tr>
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<th>Opcode/Instruction</th>
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<th>Op/En</th>
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<th>64/32 bit Mode Support</th>
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<th>CPUID Feature Flag</th>
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<th>Description</th></tr>
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<tr>
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<td>VEX.L0.66.0F3A.W1 30 /r KSHIFTRW k1, k2, imm8</td>
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<td>RRI</td>
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<td>V/V</td>
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<td>AVX512F</td>
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<td>Shift right 16 bits in k2 by immediate and write result in k1.</td></tr>
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<tr>
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<td>VEX.L0.66.0F3A.W0 30 /r KSHIFTRB k1, k2, imm8</td>
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<td>RRI</td>
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<td>V/V</td>
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<td>AVX512DQ</td>
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<td>Shift right 8 bits in k2 by immediate and write result in k1.</td></tr>
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<tr>
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<td>VEX.L0.66.0F3A.W1 31 /r KSHIFTRQ k1, k2, imm8</td>
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<td>RRI</td>
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<td>V/V</td>
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<td>AVX512BW</td>
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<td>Shift right 64 bits in k2 by immediate and write result in k1.</td></tr>
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<tr>
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<td>VEX.L0.66.0F3A.W0 31 /r KSHIFTRD k1, k2, imm8</td>
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<td>RRI</td>
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<td>V/V</td>
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<td>AVX512BW</td>
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<td>Shift right 32 bits in k2 by immediate and write result in k1.</td></tr></table>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Operand 3</th></tr>
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<tr>
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<td>RRI</td>
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<td>ModRM:reg (w)</td>
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<td>ModRM:r/m (r, ModRM:[7:6] must be 11b)</td>
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<td>imm8</td></tr></table>
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<h2 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h2>
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<p>Shifts 8/16/32/64 bits in the second operand (source operand) right by the count specified in immediate and place the least significant 8/16/32/64 bits of the result in the destination operand. The higher bits of the destination are zero-extended. The destination is set to zero if the count value is greater than 7 (for byte shift), 15 (for word shift), 31 (for doubleword shift) or 63 (for quadword shift).</p>
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<h2 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h2>
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<h3 id="kshiftrw">KSHIFTRW<a class="anchor" href="#kshiftrw">
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¶
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</a></h3>
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<pre>COUNT := imm8[7:0]
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DEST[MAX_KL-1:0] := 0
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IF COUNT <=15
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THEN DEST[15:0] := SRC1[15:0] >> COUNT;
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FI;
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</pre>
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<h3 id="kshiftrb">KSHIFTRB<a class="anchor" href="#kshiftrb">
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¶
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</a></h3>
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<pre>COUNT := imm8[7:0]
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DEST[MAX_KL-1:0] := 0
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IF COUNT <=7
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THEN DEST[7:0] := SRC1[7:0] >> COUNT;
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FI;
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</pre>
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<h3 id="kshiftrq">KSHIFTRQ<a class="anchor" href="#kshiftrq">
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¶
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</a></h3>
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<pre>COUNT := imm8[7:0]
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DEST[MAX_KL-1:0] := 0
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IF COUNT <=63
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THEN DEST[63:0] := SRC1[63:0] >> COUNT;
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FI;
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</pre>
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<h3 id="kshiftrd">KSHIFTRD<a class="anchor" href="#kshiftrd">
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¶
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</a></h3>
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<pre>COUNT := imm8[7:0]
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DEST[MAX_KL-1:0] := 0
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IF COUNT <=31
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THEN DEST[31:0] := SRC1[31:0] >> COUNT;
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FI;
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</pre>
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<h2 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
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¶
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</a></h2>
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<pre>Compiler auto generates KSHIFTRW when needed.
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</pre>
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<h2 id="flags-affected">Flags Affected<a class="anchor" href="#flags-affected">
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¶
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</a></h2>
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<p>None.</p>
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<h2 class="exceptions" id="simd-floating-point-exceptions">SIMD Floating-Point Exceptions<a class="anchor" href="#simd-floating-point-exceptions">
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¶
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</a></h2>
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<p>None.</p>
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<h2 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
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¶
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</a></h2>
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<p>See <span class="not-imported">Table 2-63</span>, “TYPE K20 Exception Definition (VEX-Encoded OpMask Instructions w/o Memory Arg).”</p><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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