117 lines
5.7 KiB
HTML
117 lines
5.7 KiB
HTML
<!DOCTYPE html>
|
||
<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>XSETBV
|
||
— Set Extended Control Register</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>XSETBV
|
||
— Set Extended Control Register</h1>
|
||
|
||
<table>
|
||
<tr>
|
||
<th>Opcode</th>
|
||
<th>Instruction</th>
|
||
<th>Op/En</th>
|
||
<th>64-Bit Mode</th>
|
||
<th>Compat/Leg Mode</th>
|
||
<th>Description</th></tr>
|
||
<tr>
|
||
<td>NP 0F 01 D1</td>
|
||
<td>XSETBV</td>
|
||
<td>ZO</td>
|
||
<td>Valid</td>
|
||
<td>Valid</td>
|
||
<td>Write the value in EDX:EAX to the XCR specified by ECX.</td></tr></table>
|
||
<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
|
||
¶
|
||
</a></h2>
|
||
<table>
|
||
<tr>
|
||
<th>Op/En</th>
|
||
<th>Operand 1</th>
|
||
<th>Operand 2</th>
|
||
<th>Operand 3</th>
|
||
<th>Operand 4</th></tr>
|
||
<tr>
|
||
<td>ZO</td>
|
||
<td>N/A</td>
|
||
<td>N/A</td>
|
||
<td>N/A</td>
|
||
<td>N/A</td></tr></table>
|
||
<h2 id="description">Description<a class="anchor" href="#description">
|
||
¶
|
||
</a></h2>
|
||
<p>Writes the contents of registers EDX:EAX into the 64-bit extended control register (XCR) specified in the ECX register. (On processors that support the Intel 64 architecture, the high-order 32 bits of RCX are ignored.) The contents of the EDX register are copied to high-order 32 bits of the selected XCR and the contents of the EAX register are copied to low-order 32 bits of the XCR. (On processors that support the Intel 64 architecture, the high-order 32 bits of each of RAX and RDX are ignored.) Undefined or reserved bits in an XCR should be set to values previously read.</p>
|
||
<p>This instruction must be executed at privilege level 0 or in real-address mode; otherwise, a general protection exception #GP(0) is generated. Specifying a reserved or unimplemented XCR in ECX will also cause a general protection exception. The processor will also generate a general protection exception if software attempts to write to reserved bits in an XCR.</p>
|
||
<p>Currently, only XCR0 is supported. Thus, all other values of ECX are reserved and will cause a #GP(0). Note that bit 0 of XCR0 (corresponding to x87 state) must be set to 1; the instruction will cause a #GP(0) if an attempt is made to clear this bit. In addition, the instruction causes a #GP(0) if an attempt is made to set XCR0[2] (AVX state) while clearing XCR0[1] (SSE state); it is necessary to set both bits to use AVX instructions; Section 13.3, “Enabling the XSAVE Feature Set and XSAVE-Enabled Features,” of Intel<sup>®</sup> 64 and IA-32 Architectures Software Developer’s Manual, Volume 1.</p>
|
||
<h2 id="operation">Operation<a class="anchor" href="#operation">
|
||
¶
|
||
</a></h2>
|
||
<pre>XCR[ECX] := EDX:EAX;
|
||
</pre>
|
||
<h2 id="flags-affected">Flags Affected<a class="anchor" href="#flags-affected">
|
||
¶
|
||
</a></h2>
|
||
<p>None.</p>
|
||
<h2 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
|
||
¶
|
||
</a></h2>
|
||
<pre>XSETBV void _xsetbv( unsigned int, unsigned __int64);
|
||
</pre>
|
||
<h2 class="exceptions" id="protected-mode-exceptions">Protected Mode Exceptions<a class="anchor" href="#protected-mode-exceptions">
|
||
¶
|
||
</a></h2>
|
||
<table>
|
||
<tr>
|
||
<td rowspan="5">#GP(0)</td>
|
||
<td>If the current privilege level is not 0.</td></tr>
|
||
<tr>
|
||
<td>If an invalid XCR is specified in ECX.</td></tr>
|
||
<tr>
|
||
<td>If the value in EDX:EAX sets bits that are reserved in the XCR specified by ECX.</td></tr>
|
||
<tr>
|
||
<td>If an attempt is made to clear bit 0 of XCR0.</td></tr>
|
||
<tr>
|
||
<td>If an attempt is made to set XCR0[2:1] to 10b.</td></tr>
|
||
<tr>
|
||
<td rowspan="3">#UD</td>
|
||
<td>If CPUID.01H:ECX.XSAVE[bit 26] = 0.</td></tr>
|
||
<tr>
|
||
<td>If CR4.OSXSAVE[bit 18] = 0.</td></tr>
|
||
<tr>
|
||
<td>If the LOCK prefix is used.</td></tr></table>
|
||
<h2 class="exceptions" id="real-address-mode-exceptions">Real-Address Mode Exceptions<a class="anchor" href="#real-address-mode-exceptions">
|
||
¶
|
||
</a></h2>
|
||
<table>
|
||
<tr>
|
||
<td rowspan="4">#GP</td>
|
||
<td>If an invalid XCR is specified in ECX.</td></tr>
|
||
<tr>
|
||
<td>If the value in EDX:EAX sets bits that are reserved in the XCR specified by ECX.</td></tr>
|
||
<tr>
|
||
<td>If an attempt is made to clear bit 0 of XCR0.</td></tr>
|
||
<tr>
|
||
<td>If an attempt is made to set XCR0[2:1] to 10b.</td></tr>
|
||
<tr>
|
||
<td rowspan="3">#UD</td>
|
||
<td>If CPUID.01H:ECX.XSAVE[bit 26] = 0.</td></tr>
|
||
<tr>
|
||
<td>If CR4.OSXSAVE[bit 18] = 0.</td></tr>
|
||
<tr>
|
||
<td>If the LOCK prefix is used.</td></tr></table>
|
||
<h2 class="exceptions" id="virtual-8086-mode-exceptions">Virtual-8086 Mode Exceptions<a class="anchor" href="#virtual-8086-mode-exceptions">
|
||
¶
|
||
</a></h2>
|
||
<table>
|
||
<tr>
|
||
<td>#GP(0)</td>
|
||
<td>The XSETBV instruction is not recognized in virtual-8086 mode.</td></tr></table>
|
||
<h2 class="exceptions" id="compatibility-mode-exceptions">Compatibility Mode Exceptions<a class="anchor" href="#compatibility-mode-exceptions">
|
||
¶
|
||
</a></h2>
|
||
<p>Same exceptions as in protected mode.</p>
|
||
<h2 class="exceptions" id="64-bit-mode-exceptions">64-Bit Mode Exceptions<a class="anchor" href="#64-bit-mode-exceptions">
|
||
¶
|
||
</a></h2>
|
||
<p>Same exceptions as in protected mode.</p><footer><p>
|
||
This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
|
||
inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
|
||
ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
|
||
</p></footer></body></html>
|